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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants
Date: Mon, 22 Oct 2018 14:57:25 +0200	[thread overview]
Message-ID: <1540213077-15211-3-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1540213077-15211-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Fredrik Noring <noring@nocrew.org>

Amend definition for MIPS ISAs in disassembler with R5900.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 disas/mips.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/disas/mips.c b/disas/mips.c
index 97f661a..ae72059 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
 /* ST Microelectronics Loongson 2F.  */
 #define INSN_LOONGSON_2F          0x80000000
 
+/* Sony/Toshiba R5900 */
+#define INSN_5900                 0x100000000
+
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
@@ -646,6 +649,7 @@ struct mips_opcode
 #define CPU_R5000	5000
 #define CPU_VR5400	5400
 #define CPU_VR5500	5500
+#define CPU_R5900       5900
 #define CPU_R6000	6000
 #define CPU_RM7000	7000
 #define CPU_R8000	8000
@@ -1193,6 +1197,7 @@ extern const int bfd_mips16_num_opcodes;
 #define N5	(INSN_5400 | INSN_5500)
 #define N54	INSN_5400
 #define N55	INSN_5500
+#define EE      INSN_5900    /* Emotion Engine */
 
 #define G1      (T3             \
                  )
@@ -3861,6 +3866,7 @@ struct mips_arch_choice
 #define bfd_mach_mips5000              5000
 #define bfd_mach_mips5400              5400
 #define bfd_mach_mips5500              5500
+#define bfd_mach_mips5900              5900
 #define bfd_mach_mips6000              6000
 #define bfd_mach_mips7000              7000
 #define bfd_mach_mips8000              8000
@@ -3908,6 +3914,8 @@ static const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "vr5500",	1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+  { "r5900",    1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
+    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "r6000",	1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
   { "rm7000",	1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
-- 
2.7.4

  parent reply	other threads:[~2018-10-22 12:58 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-22 12:57 [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants Aleksandar Markovic
2018-10-22 12:57 ` Aleksandar Markovic [this message]
2018-10-22 12:57 ` [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 " Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 24/34] tests/tcg/mips: Test R5900 three-operand MULTU Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 26/34] tests/tcg/mips: Test R5900 three-operand MULTU1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 30/34] tests/tcg/mips: Test R5900 DIVU1 Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c Aleksandar Markovic
2018-10-22 12:57 ` [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
2018-10-23 19:49 ` [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2 Peter Maydell
2018-10-23 20:37   ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
2018-10-24  8:04     ` Richard Henderson
2018-10-25 17:01       ` Fredrik Noring
2018-10-25 18:03         ` Maciej W. Rozycki
2018-10-25 18:20           ` Fredrik Noring
2018-10-26  7:26           ` Richard Henderson
2018-10-26 13:12             ` Maciej W. Rozycki

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