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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: [PATCH 2/3] drm/i915/icl: Enable ICL Pipe CSC block
Date: Wed, 24 Oct 2018 20:30:12 +0530	[thread overview]
Message-ID: <1540393213-11907-3-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1540393213-11907-1-git-send-email-uma.shankar@intel.com>

Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.

v2: Addressed Maarten's review comments.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  1 +
 drivers/gpu/drm/i915/intel_color.c | 14 ++++++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3adf689..857ce79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9700,6 +9700,7 @@ enum skl_power_gate {
 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
 #define _PIPE_A_CSC_COEFF_BV	0x49024
 #define _PIPE_A_CSC_MODE	0x49028
+#define   CSC_ENABLE			(1 << 31)
 #define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
 #define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
 #define   CSC_MODE_YUV_TO_RGB		(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 12c659f..e7042fd 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -129,7 +129,12 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
 	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
 	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
 	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
-	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		I915_WRITE(PIPE_CSC_MODE(pipe),
+			I915_READ(PIPE_CSC_MODE(pipe)) | CSC_ENABLE);
+	else
+		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 }
 
 static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
@@ -239,7 +244,11 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		if (INTEL_GEN(dev_priv) >= 11)
+			I915_WRITE(PIPE_CSC_MODE(pipe),
+				I915_READ(PIPE_CSC_MODE(pipe)) | CSC_ENABLE);
+		else
+			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 	} else {
 		uint32_t mode = CSC_MODE_YUV_TO_RGB;
 
@@ -735,6 +744,7 @@ void intel_color_init(struct drm_crtc *crtc)
 		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = glk_load_luts;
 	} else if (IS_ICELAKE(dev_priv)) {
+		dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 		dev_priv->display.load_luts = icl_load_luts;
 	} else {
 		dev_priv->display.load_luts = i9xx_load_luts;
-- 
1.9.1

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  parent reply	other threads:[~2018-10-24 14:40 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-24 15:00 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
2018-10-24 15:00 ` [PATCH 1/3] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
2018-10-31  0:03   ` Matt Roper
2018-10-31 23:40     ` Matt Roper
2018-11-01 19:07       ` Shankar, Uma
2018-10-24 15:00 ` Uma Shankar [this message]
2018-10-31 23:40   ` [PATCH 2/3] drm/i915/icl: Enable ICL Pipe CSC block Matt Roper
2018-11-01 19:15     ` Shankar, Uma
2018-10-24 15:00 ` [PATCH 3/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
2018-10-24 15:04 ` ✗ Fi.CI.CHECKPATCH: warning for Add support for Gen 11 pipe color features (rev2) Patchwork
2018-10-24 15:45 ` ✗ Fi.CI.BAT: failure " Patchwork

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