From: Andrew Murray <andrew.murray@arm.com> To: Christoffer Dall <christoffer.dall@arm.com>, Marc Zyngier <marc.zyngier@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Mark Rutland <mark.rutland@arm.com> Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/4] arm64: arm_pmu: Add support for exclude_host/exclude_guest attributes Date: Thu, 15 Nov 2018 12:55:47 +0000 [thread overview] Message-ID: <1542286549-4501-3-git-send-email-andrew.murray@arm.com> (raw) In-Reply-To: <1542286549-4501-1-git-send-email-andrew.murray@arm.com> Add support for the :G and :H attributes in perf by handling the exclude_host/exclude_guest event attributes. We notify KVM of counters that we wish to be enabled or disabled on guest entry/exit and thus defer from starting or stopping :G events as per the events exclude_host attribute. Signed-off-by: Andrew Murray <andrew.murray@arm.com> --- arch/arm64/kernel/perf_event.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 8e38d52..89d444f 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -26,6 +26,7 @@ #include <linux/acpi.h> #include <linux/clocksource.h> +#include <linux/kvm_host.h> #include <linux/of.h> #include <linux/perf/arm_pmu.h> #include <linux/platform_device.h> @@ -647,12 +648,24 @@ static inline int armv8pmu_enable_counter(int idx) static inline void armv8pmu_enable_event_counter(struct perf_event *event) { + struct perf_event_attr *attr = &event->attr; int idx = event->hw.idx; + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); - armv8pmu_enable_counter(idx); if (armv8pmu_event_is_chained(event)) - armv8pmu_enable_counter(idx - 1); - isb(); + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); + + if (attr->exclude_host) + kvm_set_clr_guest_pmu_events(0, counter_bits); + if (attr->exclude_guest) + kvm_set_clr_host_pmu_events(0, counter_bits); + + if (!attr->exclude_host) { + armv8pmu_enable_counter(idx); + if (armv8pmu_event_is_chained(event)) + armv8pmu_enable_counter(idx - 1); + isb(); + } } static inline int armv8pmu_disable_counter(int idx) @@ -665,11 +678,23 @@ static inline int armv8pmu_disable_counter(int idx) static inline void armv8pmu_disable_event_counter(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; + struct perf_event_attr *attr = &event->attr; int idx = hwc->idx; + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); if (armv8pmu_event_is_chained(event)) - armv8pmu_disable_counter(idx - 1); - armv8pmu_disable_counter(idx); + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); + + if (attr->exclude_host) + kvm_set_clr_guest_pmu_events(counter_bits, 0); + if (attr->exclude_guest) + kvm_set_clr_host_pmu_events(counter_bits, 0); + + if (!attr->exclude_host) { + if (armv8pmu_event_is_chained(event)) + armv8pmu_disable_counter(idx - 1); + armv8pmu_disable_counter(idx); + } } static inline int armv8pmu_enable_intens(int idx) @@ -977,6 +1002,10 @@ static void armv8pmu_reset(void *info) armv8pmu_disable_intens(idx); } + /* Clear the counters we flip at guest entry/exit */ + kvm_set_clr_host_pmu_events(U32_MAX, 0); + kvm_set_clr_guest_pmu_events(U32_MAX, 0); + /* * Initialize & Reset PMNC. Request overflow interrupt for * 64 bit cycle counter but cheat in armv8pmu_write_counter(). -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: andrew.murray@arm.com (Andrew Murray) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/4] arm64: arm_pmu: Add support for exclude_host/exclude_guest attributes Date: Thu, 15 Nov 2018 12:55:47 +0000 [thread overview] Message-ID: <1542286549-4501-3-git-send-email-andrew.murray@arm.com> (raw) In-Reply-To: <1542286549-4501-1-git-send-email-andrew.murray@arm.com> Add support for the :G and :H attributes in perf by handling the exclude_host/exclude_guest event attributes. We notify KVM of counters that we wish to be enabled or disabled on guest entry/exit and thus defer from starting or stopping :G events as per the events exclude_host attribute. Signed-off-by: Andrew Murray <andrew.murray@arm.com> --- arch/arm64/kernel/perf_event.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 8e38d52..89d444f 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -26,6 +26,7 @@ #include <linux/acpi.h> #include <linux/clocksource.h> +#include <linux/kvm_host.h> #include <linux/of.h> #include <linux/perf/arm_pmu.h> #include <linux/platform_device.h> @@ -647,12 +648,24 @@ static inline int armv8pmu_enable_counter(int idx) static inline void armv8pmu_enable_event_counter(struct perf_event *event) { + struct perf_event_attr *attr = &event->attr; int idx = event->hw.idx; + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); - armv8pmu_enable_counter(idx); if (armv8pmu_event_is_chained(event)) - armv8pmu_enable_counter(idx - 1); - isb(); + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); + + if (attr->exclude_host) + kvm_set_clr_guest_pmu_events(0, counter_bits); + if (attr->exclude_guest) + kvm_set_clr_host_pmu_events(0, counter_bits); + + if (!attr->exclude_host) { + armv8pmu_enable_counter(idx); + if (armv8pmu_event_is_chained(event)) + armv8pmu_enable_counter(idx - 1); + isb(); + } } static inline int armv8pmu_disable_counter(int idx) @@ -665,11 +678,23 @@ static inline int armv8pmu_disable_counter(int idx) static inline void armv8pmu_disable_event_counter(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; + struct perf_event_attr *attr = &event->attr; int idx = hwc->idx; + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); if (armv8pmu_event_is_chained(event)) - armv8pmu_disable_counter(idx - 1); - armv8pmu_disable_counter(idx); + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); + + if (attr->exclude_host) + kvm_set_clr_guest_pmu_events(counter_bits, 0); + if (attr->exclude_guest) + kvm_set_clr_host_pmu_events(counter_bits, 0); + + if (!attr->exclude_host) { + if (armv8pmu_event_is_chained(event)) + armv8pmu_disable_counter(idx - 1); + armv8pmu_disable_counter(idx); + } } static inline int armv8pmu_enable_intens(int idx) @@ -977,6 +1002,10 @@ static void armv8pmu_reset(void *info) armv8pmu_disable_intens(idx); } + /* Clear the counters we flip at guest entry/exit */ + kvm_set_clr_host_pmu_events(U32_MAX, 0); + kvm_set_clr_guest_pmu_events(U32_MAX, 0); + /* * Initialize & Reset PMNC. Request overflow interrupt for * 64 bit cycle counter but cheat in armv8pmu_write_counter(). -- 2.7.4
next prev parent reply other threads:[~2018-11-15 12:55 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-15 12:55 [PATCH 0/4] arm64: Support perf event modifiers :G and :H Andrew Murray 2018-11-15 12:55 ` Andrew Murray 2018-11-15 12:55 ` [PATCH 1/4] arm64: KVM: add accessors to track guest/host only counters Andrew Murray 2018-11-15 12:55 ` Andrew Murray 2018-11-15 12:55 ` Andrew Murray [this message] 2018-11-15 12:55 ` [PATCH 2/4] arm64: arm_pmu: Add support for exclude_host/exclude_guest attributes Andrew Murray 2018-11-15 12:55 ` [PATCH 3/4] arm64: arm_pmu: Exclude EL1,2 with :G :H perf attributes Andrew Murray 2018-11-15 12:55 ` Andrew Murray 2018-11-15 14:57 ` Suzuki K Poulose 2018-11-15 14:57 ` Suzuki K Poulose 2018-11-15 16:06 ` Andrew Murray 2018-11-15 16:06 ` Andrew Murray 2018-11-15 12:55 ` [PATCH 4/4] arm64: KVM: Enable support for :G/:H perf event modifiers Andrew Murray 2018-11-15 12:55 ` Andrew Murray 2018-11-15 14:00 ` Julien Thierry 2018-11-15 14:00 ` Julien Thierry 2018-11-15 15:57 ` Andrew Murray 2018-11-15 15:57 ` Andrew Murray 2018-11-15 17:40 ` Suzuki K Poulose 2018-11-15 17:40 ` Suzuki K Poulose 2018-11-16 12:12 ` Andrew Murray 2018-11-16 12:12 ` Andrew Murray 2018-11-16 17:53 ` Suzuki K Poulose 2018-11-16 17:53 ` Suzuki K Poulose
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1542286549-4501-3-git-send-email-andrew.murray@arm.com \ --to=andrew.murray@arm.com \ --cc=catalin.marinas@arm.com \ --cc=christoffer.dall@arm.com \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=marc.zyngier@arm.com \ --cc=mark.rutland@arm.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.