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From: Anson Huang <anson.huang@nxp.com>
To: "shawnguo@kernel.org" <shawnguo@kernel.org>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	Aisheng Dong <aisheng.dong@nxp.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Cc: dl-linux-imx <linux-imx@nxp.com>
Subject: [PATCH 3/3] ARM: dts: imx7ulp: add HSRUN mode clocks
Date: Fri, 7 Dec 2018 10:03:39 +0000	[thread overview]
Message-ID: <1544176659-32022-3-git-send-email-Anson.Huang@nxp.com> (raw)
In-Reply-To: <1544176659-32022-1-git-send-email-Anson.Huang@nxp.com>

i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
This patch is based on top of path series: [V5,1/6] dt-bindings: fsl: add compatible for imx7ulp evk,
https://patchwork.kernel.org/patch/10677263/
---
 arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b275..b86daf7 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@
 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 		};
 
-		smc1: smc1@40410000 {
+		smc1: clock-controller@40410000 {
 			compatible = "fsl,imx7ulp-smc1";
 			reg = <0x40410000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+			clock-names = "divcore", "hsrun_divcore";
 		};
 
 		pcc3: clock-controller@40b30000 {
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Anson Huang <anson.huang@nxp.com>
To: "shawnguo@kernel.org" <shawnguo@kernel.org>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	Aisheng Dong <aisheng.dong@nxp.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Cc: dl-linux-imx <linux-imx@nxp.com>
Subject: [PATCH 3/3] ARM: dts: imx7ulp: add HSRUN mode clocks
Date: Fri, 7 Dec 2018 10:03:39 +0000	[thread overview]
Message-ID: <1544176659-32022-3-git-send-email-Anson.Huang@nxp.com> (raw)
In-Reply-To: <1544176659-32022-1-git-send-email-Anson.Huang@nxp.com>

i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
This patch is based on top of path series: [V5,1/6] dt-bindings: fsl: add compatible for imx7ulp evk,
https://patchwork.kernel.org/patch/10677263/
---
 arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b275..b86daf7 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@
 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 		};
 
-		smc1: smc1@40410000 {
+		smc1: clock-controller@40410000 {
 			compatible = "fsl,imx7ulp-smc1";
 			reg = <0x40410000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+			clock-names = "divcore", "hsrun_divcore";
 		};
 
 		pcc3: clock-controller@40b30000 {
-- 
2.7.4


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  parent reply	other threads:[~2018-12-07 10:03 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-07 10:03 [PATCH 1/3] dt-bindings: clock: imx7ulp: add HSRUN mode related clocks Anson Huang
2018-12-07 10:03 ` Anson Huang
2018-12-07 10:03 ` Anson Huang
2018-12-07 10:03 ` [PATCH 2/3] clk: imx: imx7ulp: add arm hsrun mode clocks support Anson Huang
2018-12-07 10:03   ` Anson Huang
2018-12-07 10:03   ` Anson Huang
2018-12-14 22:04   ` Stephen Boyd
2018-12-14 22:04     ` Stephen Boyd
2018-12-14 22:04     ` Stephen Boyd
2018-12-07 10:03 ` Anson Huang [this message]
2018-12-07 10:03   ` [PATCH 3/3] ARM: dts: imx7ulp: add HSRUN mode clocks Anson Huang
2018-12-07 10:03   ` Anson Huang
2019-01-10  6:56   ` Shawn Guo
2019-01-10  6:56     ` Shawn Guo
2019-01-10  6:56     ` Shawn Guo
2018-12-14 22:04 ` [PATCH 1/3] dt-bindings: clock: imx7ulp: add HSRUN mode related clocks Stephen Boyd
2018-12-14 22:04   ` Stephen Boyd
2018-12-14 22:04   ` Stephen Boyd

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