From: cezary.gapinski@gmail.com To: Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@st.com>, Amelie Delaunay <amelie.delaunay@st.com>, Mark Rutland <mark.rutland@arm.com>, Cezary Gapinski <cezary.gapinski@gmail.com> Subject: [PATCH 1/5] spi: stm32: rename STM32 SPI registers and functions to STM32H7 Date: Sun, 9 Dec 2018 14:53:52 +0100 [thread overview] Message-ID: <1544363636-12161-2-git-send-email-cezary.gapinski@gmail.com> (raw) In-Reply-To: <1544363636-12161-1-git-send-email-cezary.gapinski@gmail.com> From: Cezary Gapinski <cezary.gapinski@gmail.com> Rename STM32 SPI registers and functions to be related to STM32H7 SPI driver and not STM32 generally. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> --- drivers/spi/spi-stm32.c | 662 +++++++++++++++++++++++++----------------------- 1 file changed, 340 insertions(+), 322 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index ad1e55d..eb4d93e 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -33,97 +33,97 @@ #define DRIVER_NAME "spi_stm32" -/* STM32 SPI registers */ -#define STM32_SPI_CR1 0x00 -#define STM32_SPI_CR2 0x04 -#define STM32_SPI_CFG1 0x08 -#define STM32_SPI_CFG2 0x0C -#define STM32_SPI_IER 0x10 -#define STM32_SPI_SR 0x14 -#define STM32_SPI_IFCR 0x18 -#define STM32_SPI_TXDR 0x20 -#define STM32_SPI_RXDR 0x30 -#define STM32_SPI_I2SCFGR 0x50 - -/* STM32_SPI_CR1 bit fields */ -#define SPI_CR1_SPE BIT(0) -#define SPI_CR1_MASRX BIT(8) -#define SPI_CR1_CSTART BIT(9) -#define SPI_CR1_CSUSP BIT(10) -#define SPI_CR1_HDDIR BIT(11) -#define SPI_CR1_SSI BIT(12) - -/* STM32_SPI_CR2 bit fields */ -#define SPI_CR2_TSIZE_SHIFT 0 -#define SPI_CR2_TSIZE GENMASK(15, 0) - -/* STM32_SPI_CFG1 bit fields */ -#define SPI_CFG1_DSIZE_SHIFT 0 -#define SPI_CFG1_DSIZE GENMASK(4, 0) -#define SPI_CFG1_FTHLV_SHIFT 5 -#define SPI_CFG1_FTHLV GENMASK(8, 5) -#define SPI_CFG1_RXDMAEN BIT(14) -#define SPI_CFG1_TXDMAEN BIT(15) -#define SPI_CFG1_MBR_SHIFT 28 -#define SPI_CFG1_MBR GENMASK(30, 28) -#define SPI_CFG1_MBR_MIN 0 -#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) - -/* STM32_SPI_CFG2 bit fields */ -#define SPI_CFG2_MIDI_SHIFT 4 -#define SPI_CFG2_MIDI GENMASK(7, 4) -#define SPI_CFG2_COMM_SHIFT 17 -#define SPI_CFG2_COMM GENMASK(18, 17) -#define SPI_CFG2_SP_SHIFT 19 -#define SPI_CFG2_SP GENMASK(21, 19) -#define SPI_CFG2_MASTER BIT(22) -#define SPI_CFG2_LSBFRST BIT(23) -#define SPI_CFG2_CPHA BIT(24) -#define SPI_CFG2_CPOL BIT(25) -#define SPI_CFG2_SSM BIT(26) -#define SPI_CFG2_AFCNTR BIT(31) - -/* STM32_SPI_IER bit fields */ -#define SPI_IER_RXPIE BIT(0) -#define SPI_IER_TXPIE BIT(1) -#define SPI_IER_DXPIE BIT(2) -#define SPI_IER_EOTIE BIT(3) -#define SPI_IER_TXTFIE BIT(4) -#define SPI_IER_OVRIE BIT(6) -#define SPI_IER_MODFIE BIT(9) -#define SPI_IER_ALL GENMASK(10, 0) - -/* STM32_SPI_SR bit fields */ -#define SPI_SR_RXP BIT(0) -#define SPI_SR_TXP BIT(1) -#define SPI_SR_EOT BIT(3) -#define SPI_SR_OVR BIT(6) -#define SPI_SR_MODF BIT(9) -#define SPI_SR_SUSP BIT(11) -#define SPI_SR_RXPLVL_SHIFT 13 -#define SPI_SR_RXPLVL GENMASK(14, 13) -#define SPI_SR_RXWNE BIT(15) - -/* STM32_SPI_IFCR bit fields */ -#define SPI_IFCR_ALL GENMASK(11, 3) - -/* STM32_SPI_I2SCFGR bit fields */ -#define SPI_I2SCFGR_I2SMOD BIT(0) - -/* SPI Master Baud Rate min/max divisor */ -#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN) -#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX) - -/* SPI Communication mode */ -#define SPI_FULL_DUPLEX 0 -#define SPI_SIMPLEX_TX 1 -#define SPI_SIMPLEX_RX 2 -#define SPI_HALF_DUPLEX 3 - -#define SPI_1HZ_NS 1000000000 +/* STM32H7 SPI registers */ +#define STM32H7_SPI_CR1 0x00 +#define STM32H7_SPI_CR2 0x04 +#define STM32H7_SPI_CFG1 0x08 +#define STM32H7_SPI_CFG2 0x0C +#define STM32H7_SPI_IER 0x10 +#define STM32H7_SPI_SR 0x14 +#define STM32H7_SPI_IFCR 0x18 +#define STM32H7_SPI_TXDR 0x20 +#define STM32H7_SPI_RXDR 0x30 +#define STM32H7_SPI_I2SCFGR 0x50 + +/* STM32H7_SPI_CR1 bit fields */ +#define STM32H7_SPI_CR1_SPE BIT(0) +#define STM32H7_SPI_CR1_MASRX BIT(8) +#define STM32H7_SPI_CR1_CSTART BIT(9) +#define STM32H7_SPI_CR1_CSUSP BIT(10) +#define STM32H7_SPI_CR1_HDDIR BIT(11) +#define STM32H7_SPI_CR1_SSI BIT(12) + +/* STM32H7_SPI_CR2 bit fields */ +#define STM32H7_SPI_CR2_TSIZE_SHIFT 0 +#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) + +/* STM32H7_SPI_CFG1 bit fields */ +#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 +#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) +#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 +#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) +#define STM32H7_SPI_CFG1_RXDMAEN BIT(14) +#define STM32H7_SPI_CFG1_TXDMAEN BIT(15) +#define STM32H7_SPI_CFG1_MBR_SHIFT 28 +#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) +#define STM32H7_SPI_CFG1_MBR_MIN 0 +#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) + +/* STM32H7_SPI_CFG2 bit fields */ +#define STM32H7_SPI_CFG2_MIDI_SHIFT 4 +#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) +#define STM32H7_SPI_CFG2_COMM_SHIFT 17 +#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) +#define STM32H7_SPI_CFG2_SP_SHIFT 19 +#define STM32H7_SPI_CFG2_SP GENMASK(21, 19) +#define STM32H7_SPI_CFG2_MASTER BIT(22) +#define STM32H7_SPI_CFG2_LSBFRST BIT(23) +#define STM32H7_SPI_CFG2_CPHA BIT(24) +#define STM32H7_SPI_CFG2_CPOL BIT(25) +#define STM32H7_SPI_CFG2_SSM BIT(26) +#define STM32H7_SPI_CFG2_AFCNTR BIT(31) + +/* STM32H7_SPI_IER bit fields */ +#define STM32H7_SPI_IER_RXPIE BIT(0) +#define STM32H7_SPI_IER_TXPIE BIT(1) +#define STM32H7_SPI_IER_DXPIE BIT(2) +#define STM32H7_SPI_IER_EOTIE BIT(3) +#define STM32H7_SPI_IER_TXTFIE BIT(4) +#define STM32H7_SPI_IER_OVRIE BIT(6) +#define STM32H7_SPI_IER_MODFIE BIT(9) +#define STM32H7_SPI_IER_ALL GENMASK(10, 0) + +/* STM32H7_SPI_SR bit fields */ +#define STM32H7_SPI_SR_RXP BIT(0) +#define STM32H7_SPI_SR_TXP BIT(1) +#define STM32H7_SPI_SR_EOT BIT(3) +#define STM32H7_SPI_SR_OVR BIT(6) +#define STM32H7_SPI_SR_MODF BIT(9) +#define STM32H7_SPI_SR_SUSP BIT(11) +#define STM32H7_SPI_SR_RXPLVL_SHIFT 13 +#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) +#define STM32H7_SPI_SR_RXWNE BIT(15) + +/* STM32H7_SPI_IFCR bit fields */ +#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) + +/* STM32H7_SPI_I2SCFGR bit fields */ +#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) + +/* STM32H7 SPI Master Baud Rate min/max divisor */ +#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) +#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) + +/* STM32H7 SPI Communication mode */ +#define STM32H7_SPI_FULL_DUPLEX 0 +#define STM32H7_SPI_SIMPLEX_TX 1 +#define STM32H7_SPI_SIMPLEX_RX 2 +#define STM32H7_SPI_HALF_DUPLEX 3 + +#define STM32H7_SPI_1HZ_NS 1000000000 /** - * struct stm32_spi - private data of the SPI controller + * struct stm32h7_spi - private data of the SPI controller * @dev: driver model representation of the controller * @master: controller master interface * @base: virtual memory area @@ -148,7 +148,7 @@ * @dma_rx: dma channel for RX transfer * @phys_addr: SPI registers physical base address */ -struct stm32_spi { +struct stm32h7_spi { struct device *dev; struct spi_master *master; void __iomem *base; @@ -176,37 +176,37 @@ struct stm32_spi { dma_addr_t phys_addr; }; -static inline void stm32_spi_set_bits(struct stm32_spi *spi, - u32 offset, u32 bits) +static inline void stm32h7_spi_set_bits(struct stm32h7_spi *spi, + u32 offset, u32 bits) { writel_relaxed(readl_relaxed(spi->base + offset) | bits, spi->base + offset); } -static inline void stm32_spi_clr_bits(struct stm32_spi *spi, - u32 offset, u32 bits) +static inline void stm32h7_spi_clr_bits(struct stm32h7_spi *spi, + u32 offset, u32 bits) { writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, spi->base + offset); } /** - * stm32_spi_get_fifo_size - Return fifo size + * stm32h7_spi_get_fifo_size - Return fifo size * @spi: pointer to the spi controller data structure */ -static int stm32_spi_get_fifo_size(struct stm32_spi *spi) +static int stm32h7_spi_get_fifo_size(struct stm32h7_spi *spi) { unsigned long flags; u32 count = 0; spin_lock_irqsave(&spi->lock, flags); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); - while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP) - writeb_relaxed(++count, spi->base + STM32_SPI_TXDR); + while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) + writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); spin_unlock_irqrestore(&spi->lock, flags); @@ -216,10 +216,10 @@ static int stm32_spi_get_fifo_size(struct stm32_spi *spi) } /** - * stm32_spi_get_bpw_mask - Return bits per word mask + * stm32h7_spi_get_bpw_mask - Return bits per word mask * @spi: pointer to the spi controller data structure */ -static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) +static int stm32h7_spi_get_bpw_mask(struct stm32h7_spi *spi) { unsigned long flags; u32 cfg1, max_bpw; @@ -230,10 +230,11 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) * The most significant bit at DSIZE bit field is reserved when the * maximum data size of periperal instances is limited to 16-bit */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); - cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1); - max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT; + cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); + max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> + STM32H7_SPI_CFG1_DSIZE_SHIFT; max_bpw += 1; spin_unlock_irqrestore(&spi->lock, flags); @@ -244,13 +245,13 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) } /** - * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value + * stm32h7_spi_prepare_mbr - Determine STM32H7_SPI_CFG1.MBR value * @spi: pointer to the spi controller data structure * @speed_hz: requested speed * - * Return SPI_CFG1.MBR value in case of success or -EINVAL + * Return STM32H7_SPI_CFG1.MBR value in case of success or -EINVAL */ -static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) +static int stm32h7_spi_prepare_mbr(struct stm32h7_spi *spi, u32 speed_hz) { u32 div, mbrdiv; @@ -263,8 +264,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) * no need to check it there. * However, we need to ensure the following calculations. */ - if (div < SPI_MBR_DIV_MIN || - div > SPI_MBR_DIV_MAX) + if (div < STM32H7_SPI_MBR_DIV_MIN || + div > STM32H7_SPI_MBR_DIV_MAX) return -EINVAL; /* Determine the first power of 2 greater than or equal to div */ @@ -279,10 +280,10 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) } /** - * stm32_spi_prepare_fthlv - Determine FIFO threshold level + * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level * @spi: pointer to the spi controller data structure */ -static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi) +static u32 stm32h7_spi_prepare_fthlv(struct stm32h7_spi *spi) { u32 fthlv, half_fifo; @@ -306,32 +307,33 @@ static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi) } /** - * stm32_spi_write_txfifo - Write bytes in Transmit Data Register + * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register * @spi: pointer to the spi controller data structure * * Read from tx_buf depends on remaining bytes to avoid to read beyond * tx_buf end. */ -static void stm32_spi_write_txfifo(struct stm32_spi *spi) +static void stm32h7_spi_write_txfifo(struct stm32h7_spi *spi) { while ((spi->tx_len > 0) && - (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) { + (readl_relaxed(spi->base + STM32H7_SPI_SR) & + STM32H7_SPI_SR_TXP)) { u32 offs = spi->cur_xferlen - spi->tx_len; if (spi->tx_len >= sizeof(u32)) { const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); - writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR); + writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u32); } else if (spi->tx_len >= sizeof(u16)) { const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); - writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR); + writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u16); } else { const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); - writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR); + writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u8); } } @@ -340,43 +342,45 @@ static void stm32_spi_write_txfifo(struct stm32_spi *spi) } /** - * stm32_spi_read_rxfifo - Read bytes in Receive Data Register + * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register * @spi: pointer to the spi controller data structure * * Write in rx_buf depends on remaining bytes to avoid to write beyond * rx_buf end. */ -static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush) +static void stm32h7_spi_read_rxfifo(struct stm32h7_spi *spi, bool flush) { - u32 sr = readl_relaxed(spi->base + STM32_SPI_SR); - u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> + STM32H7_SPI_SR_RXPLVL_SHIFT; while ((spi->rx_len > 0) && - ((sr & SPI_SR_RXP) || - (flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) { + ((sr & STM32H7_SPI_SR_RXP) || + (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { u32 offs = spi->cur_xferlen - spi->rx_len; if ((spi->rx_len >= sizeof(u32)) || - (flush && (sr & SPI_SR_RXWNE))) { + (flush && (sr & STM32H7_SPI_SR_RXWNE))) { u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); - *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u32); } else if ((spi->rx_len >= sizeof(u16)) || (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); - *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u16); } else { u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); - *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u8); } - sr = readl_relaxed(spi->base + STM32_SPI_SR); - rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> + STM32H7_SPI_SR_RXPLVL_SHIFT; } dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, @@ -384,28 +388,28 @@ static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush) } /** - * stm32_spi_enable - Enable SPI controller + * stm32h7_spi_enable - Enable SPI controller * @spi: pointer to the spi controller data structure * * SPI data transfer is enabled but spi_ker_ck is idle. - * SPI_CFG1 and SPI_CFG2 are now write protected. + * STM32H7_SPI_CFG1 and STM32H7_SPI_CFG2 are now write protected. */ -static void stm32_spi_enable(struct stm32_spi *spi) +static void stm32h7_spi_enable(struct stm32h7_spi *spi) { dev_dbg(spi->dev, "enable controller\n"); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); } /** - * stm32_spi_disable - Disable SPI controller + * stm32h7_spi_disable - Disable SPI controller * @spi: pointer to the spi controller data structure * * RX-Fifo is flushed when SPI controller is disabled. To prevent any data - * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in + * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in * RX-Fifo. */ -static void stm32_spi_disable(struct stm32_spi *spi) +static void stm32h7_spi_disable(struct stm32h7_spi *spi) { unsigned long flags; u32 cr1, sr; @@ -414,23 +418,23 @@ static void stm32_spi_disable(struct stm32_spi *spi) spin_lock_irqsave(&spi->lock, flags); - cr1 = readl_relaxed(spi->base + STM32_SPI_CR1); + cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); - if (!(cr1 & SPI_CR1_SPE)) { + if (!(cr1 & STM32H7_SPI_CR1_SPE)) { spin_unlock_irqrestore(&spi->lock, flags); return; } /* Wait on EOT or suspend the flow */ - if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR, - sr, !(sr & SPI_SR_EOT), + if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, + sr, !(sr & STM32H7_SPI_SR_EOT), 10, 100000) < 0) { - if (cr1 & SPI_CR1_CSTART) { - writel_relaxed(cr1 | SPI_CR1_CSUSP, - spi->base + STM32_SPI_CR1); + if (cr1 & STM32H7_SPI_CR1_CSTART) { + writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, + spi->base + STM32H7_SPI_CR1); if (readl_relaxed_poll_timeout_atomic( - spi->base + STM32_SPI_SR, - sr, !(sr & SPI_SR_SUSP), + spi->base + STM32H7_SPI_SR, + sr, !(sr & STM32H7_SPI_SR_SUSP), 10, 100000) < 0) dev_warn(spi->dev, "Suspend request timeout\n"); @@ -438,35 +442,35 @@ static void stm32_spi_disable(struct stm32_spi *spi) } if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) - stm32_spi_read_rxfifo(spi, true); + stm32h7_spi_read_rxfifo(spi, true); if (spi->cur_usedma && spi->tx_buf) dmaengine_terminate_all(spi->dma_tx); if (spi->cur_usedma && spi->rx_buf) dmaengine_terminate_all(spi->dma_rx); - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); - stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN | - SPI_CFG1_RXDMAEN); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | + STM32H7_SPI_CFG1_RXDMAEN); /* Disable interrupts and clear status flags */ - writel_relaxed(0, spi->base + STM32_SPI_IER); - writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR); + writel_relaxed(0, spi->base + STM32H7_SPI_IER); + writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); spin_unlock_irqrestore(&spi->lock, flags); } /** - * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use + * stm32h7_spi_can_dma - Determine if the transfer is eligible for DMA use * * If the current transfer size is greater than fifo size, use DMA. */ -static bool stm32_spi_can_dma(struct spi_master *master, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static bool stm32h7_spi_can_dma(struct spi_master *master, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); dev_dbg(spi->dev, "%s: %s\n", __func__, (transfer->len > spi->fifo_size) ? "true" : "false"); @@ -475,33 +479,33 @@ static bool stm32_spi_can_dma(struct spi_master *master, } /** - * stm32_spi_irq - Interrupt handler for SPI controller events + * stm32h7_spi_irq - Interrupt handler for SPI controller events * @irq: interrupt line * @dev_id: SPI controller master interface */ -static irqreturn_t stm32_spi_irq(int irq, void *dev_id) +static irqreturn_t stm32h7_spi_irq(int irq, void *dev_id) { struct spi_master *master = dev_id; - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); u32 sr, ier, mask; unsigned long flags; bool end = false; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32_SPI_SR); - ier = readl_relaxed(spi->base + STM32_SPI_IER); + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + ier = readl_relaxed(spi->base + STM32H7_SPI_IER); mask = ier; /* EOTIE is triggered on EOT, SUSP and TXC events. */ - mask |= SPI_SR_SUSP; + mask |= STM32H7_SPI_SR_SUSP; /* * When TXTF is set, DXPIE and TXPIE are cleared. So in case of * Full-Duplex, need to poll RXP event to know if there are remaining * data, before disabling SPI. */ if (spi->rx_buf && !spi->cur_usedma) - mask |= SPI_SR_RXP; + mask |= STM32H7_SPI_SR_RXP; if (!(sr & mask)) { dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", @@ -510,10 +514,10 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) return IRQ_NONE; } - if (sr & SPI_SR_SUSP) { + if (sr & STM32H7_SPI_SR_SUSP) { dev_warn(spi->dev, "Communication suspended\n"); if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); /* * If communication is suspended while using DMA, it means * that something went wrong, so stop the current transfer @@ -522,15 +526,15 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) end = true; } - if (sr & SPI_SR_MODF) { + if (sr & STM32H7_SPI_SR_MODF) { dev_warn(spi->dev, "Mode fault: transfer aborted\n"); end = true; } - if (sr & SPI_SR_OVR) { + if (sr & STM32H7_SPI_SR_OVR) { dev_warn(spi->dev, "Overrun: received value discarded\n"); if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); /* * If overrun is detected while using DMA, it means that * something went wrong, so stop the current transfer @@ -539,36 +543,36 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) end = true; } - if (sr & SPI_SR_EOT) { + if (sr & STM32H7_SPI_SR_EOT) { if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, true); + stm32h7_spi_read_rxfifo(spi, true); end = true; } - if (sr & SPI_SR_TXP) + if (sr & STM32H7_SPI_SR_TXP) if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) - stm32_spi_write_txfifo(spi); + stm32h7_spi_write_txfifo(spi); - if (sr & SPI_SR_RXP) + if (sr & STM32H7_SPI_SR_RXP) if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); - writel_relaxed(mask, spi->base + STM32_SPI_IFCR); + writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); spin_unlock_irqrestore(&spi->lock, flags); if (end) { spi_finalize_current_transfer(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); } return IRQ_HANDLED; } /** - * stm32_spi_setup - setup device chip select + * stm32h7_spi_setup - setup device chip select */ -static int stm32_spi_setup(struct spi_device *spi_dev) +static int stm32h7_spi_setup(struct spi_device *spi_dev) { int ret = 0; @@ -589,12 +593,12 @@ static int stm32_spi_setup(struct spi_device *spi_dev) } /** - * stm32_spi_prepare_msg - set up the controller to transfer a single message + * stm32h7_spi_prepare_msg - set up the controller to transfer a single message */ -static int stm32_spi_prepare_msg(struct spi_master *master, - struct spi_message *msg) +static int stm32h7_spi_prepare_msg(struct spi_master *master, + struct spi_message *msg) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); struct spi_device *spi_dev = msg->spi; struct device_node *np = spi_dev->dev.of_node; unsigned long flags; @@ -606,19 +610,19 @@ static int stm32_spi_prepare_msg(struct spi_master *master, dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); if (spi_dev->mode & SPI_CPOL) - cfg2_setb |= SPI_CFG2_CPOL; + cfg2_setb |= STM32H7_SPI_CFG2_CPOL; else - cfg2_clrb |= SPI_CFG2_CPOL; + cfg2_clrb |= STM32H7_SPI_CFG2_CPOL; if (spi_dev->mode & SPI_CPHA) - cfg2_setb |= SPI_CFG2_CPHA; + cfg2_setb |= STM32H7_SPI_CFG2_CPHA; else - cfg2_clrb |= SPI_CFG2_CPHA; + cfg2_clrb |= STM32H7_SPI_CFG2_CPHA; if (spi_dev->mode & SPI_LSB_FIRST) - cfg2_setb |= SPI_CFG2_LSBFRST; + cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST; else - cfg2_clrb |= SPI_CFG2_LSBFRST; + cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST; dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", spi_dev->mode & SPI_CPOL, @@ -630,9 +634,9 @@ static int stm32_spi_prepare_msg(struct spi_master *master, if (cfg2_clrb || cfg2_setb) writel_relaxed( - (readl_relaxed(spi->base + STM32_SPI_CFG2) & + (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & ~cfg2_clrb) | cfg2_setb, - spi->base + STM32_SPI_CFG2); + spi->base + STM32H7_SPI_CFG2); spin_unlock_irqrestore(&spi->lock, flags); @@ -640,36 +644,36 @@ static int stm32_spi_prepare_msg(struct spi_master *master, } /** - * stm32_spi_dma_cb - dma callback + * stm32h7_spi_dma_cb - dma callback * * DMA callback is called when the transfer is complete or when an error * occurs. If the transfer is complete, EOT flag is raised. */ -static void stm32_spi_dma_cb(void *data) +static void stm32h7_spi_dma_cb(void *data) { - struct stm32_spi *spi = data; + struct stm32h7_spi *spi = data; unsigned long flags; u32 sr; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32_SPI_SR); + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); spin_unlock_irqrestore(&spi->lock, flags); - if (!(sr & SPI_SR_EOT)) + if (!(sr & STM32H7_SPI_SR_EOT)) dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); /* Now wait for EOT, or SUSP or OVR in case of error */ } /** - * stm32_spi_dma_config - configure dma slave channel depending on current - * transfer bits_per_word. + * stm32h7_spi_dma_config - configure dma slave channel depending on current + * transfer bits_per_word. */ -static void stm32_spi_dma_config(struct stm32_spi *spi, - struct dma_slave_config *dma_conf, - enum dma_transfer_direction dir) +static void stm32h7_spi_dma_config(struct stm32h7_spi *spi, + struct dma_slave_config *dma_conf, + enum dma_transfer_direction dir) { enum dma_slave_buswidth buswidth; u32 maxburst; @@ -690,14 +694,14 @@ static void stm32_spi_dma_config(struct stm32_spi *spi, memset(dma_conf, 0, sizeof(struct dma_slave_config)); dma_conf->direction = dir; if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ - dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR; + dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR; dma_conf->src_addr_width = buswidth; dma_conf->src_maxburst = maxburst; dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", buswidth, maxburst); } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ - dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR; + dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR; dma_conf->dst_addr_width = buswidth; dma_conf->dst_maxburst = maxburst; @@ -707,39 +711,40 @@ static void stm32_spi_dma_config(struct stm32_spi *spi, } /** - * stm32_spi_transfer_one_irq - transfer a single spi_transfer using - * interrupts + * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using + * interrupts * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one_irq(struct stm32_spi *spi) +static int stm32h7_spi_transfer_one_irq(struct stm32h7_spi *spi) { unsigned long flags; u32 ier = 0; /* Enable the interrupts relative to the current communication mode */ if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ - ier |= SPI_IER_DXPIE; + ier |= STM32H7_SPI_IER_DXPIE; else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ - ier |= SPI_IER_TXPIE; + ier |= STM32H7_SPI_IER_TXPIE; else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ - ier |= SPI_IER_RXPIE; + ier |= STM32H7_SPI_IER_RXPIE; /* Enable the interrupts relative to the end of transfer */ - ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE; + ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | + STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; spin_lock_irqsave(&spi->lock, flags); - stm32_spi_enable(spi); + stm32h7_spi_enable(spi); /* Be sure to have data in fifo before starting data transfer */ if (spi->tx_buf) - stm32_spi_write_txfifo(spi); + stm32h7_spi_write_txfifo(spi); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); - writel_relaxed(ier, spi->base + STM32_SPI_IER); + writel_relaxed(ier, spi->base + STM32H7_SPI_IER); spin_unlock_irqrestore(&spi->lock, flags); @@ -747,13 +752,13 @@ static int stm32_spi_transfer_one_irq(struct stm32_spi *spi) } /** - * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA + * stm32h7_spi_transfer_one_dma - transfer a single spi_transfer using DMA * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, - struct spi_transfer *xfer) +static int stm32h7_spi_transfer_one_dma(struct stm32h7_spi *spi, + struct spi_transfer *xfer) { struct dma_slave_config tx_dma_conf, rx_dma_conf; struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; @@ -764,11 +769,12 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, rx_dma_desc = NULL; if (spi->rx_buf) { - stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); + stm32h7_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); /* Enable Rx DMA request */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, + STM32H7_SPI_CFG1_RXDMAEN); rx_dma_desc = dmaengine_prep_slave_sg( spi->dma_rx, xfer->rx_sg.sgl, @@ -779,7 +785,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, tx_dma_desc = NULL; if (spi->tx_buf) { - stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); + stm32h7_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); tx_dma_desc = dmaengine_prep_slave_sg( @@ -794,7 +800,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, goto dma_desc_error; if (rx_dma_desc) { - rx_dma_desc->callback = stm32_spi_dma_cb; + rx_dma_desc->callback = stm32h7_spi_dma_cb; rx_dma_desc->callback_param = spi; if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { @@ -806,8 +812,8 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, } if (tx_dma_desc) { - if (spi->cur_comm == SPI_SIMPLEX_TX) { - tx_dma_desc->callback = stm32_spi_dma_cb; + if (spi->cur_comm == STM32H7_SPI_SIMPLEX_TX) { + tx_dma_desc->callback = stm32h7_spi_dma_cb; tx_dma_desc->callback_param = spi; } @@ -819,16 +825,18 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, dma_async_issue_pending(spi->dma_tx); /* Enable Tx DMA request */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, + STM32H7_SPI_CFG1_TXDMAEN); } /* Enable the interrupts relative to the end of transfer */ - ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE; - writel_relaxed(ier, spi->base + STM32_SPI_IER); + ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | + STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; + writel_relaxed(ier, spi->base + STM32H7_SPI_IER); - stm32_spi_enable(spi); + stm32h7_spi_enable(spi); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); spin_unlock_irqrestore(&spi->lock, flags); @@ -839,23 +847,23 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, dmaengine_terminate_all(spi->dma_rx); dma_desc_error: - stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN); spin_unlock_irqrestore(&spi->lock, flags); dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); - return stm32_spi_transfer_one_irq(spi); + return stm32h7_spi_transfer_one_irq(spi); } /** - * stm32_spi_transfer_one_setup - common setup to transfer a single - * spi_transfer either using DMA or - * interrupts. + * stm32h7_spi_transfer_one_setup - common setup to transfer a single + * spi_transfer either using DMA or + * interrupts. */ -static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static int stm32h7_spi_transfer_one_setup(struct stm32h7_spi *spi, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { unsigned long flags; u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0; @@ -870,21 +878,23 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, spi->cur_bpw = transfer->bits_per_word; bpw = spi->cur_bpw - 1; - cfg1_clrb |= SPI_CFG1_DSIZE; - cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE; + cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; + cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & + STM32H7_SPI_CFG1_DSIZE; - spi->cur_fthlv = stm32_spi_prepare_fthlv(spi); + spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi); fthlv = spi->cur_fthlv - 1; - cfg1_clrb |= SPI_CFG1_FTHLV; - cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV; + cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; + cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & + STM32H7_SPI_CFG1_FTHLV; } if (spi->cur_speed != transfer->speed_hz) { int mbr; /* Update spi->cur_speed with real clock speed */ - mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz); + mbr = stm32h7_spi_prepare_mbr(spi, transfer->speed_hz); if (mbr < 0) { ret = mbr; goto out; @@ -892,16 +902,17 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, transfer->speed_hz = spi->cur_speed; - cfg1_clrb |= SPI_CFG1_MBR; - cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR; + cfg1_clrb |= STM32H7_SPI_CFG1_MBR; + cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) & + STM32H7_SPI_CFG1_MBR; } if (cfg1_clrb || cfg1_setb) - writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) & + writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) & ~cfg1_clrb) | cfg1_setb, - spi->base + STM32_SPI_CFG1); + spi->base + STM32H7_SPI_CFG1); - mode = SPI_FULL_DUPLEX; + mode = STM32H7_SPI_FULL_DUPLEX; if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ /* * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL @@ -909,40 +920,46 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, * on the valid buffer, we can determine the direction of the * transfer. */ - mode = SPI_HALF_DUPLEX; + mode = STM32H7_SPI_HALF_DUPLEX; if (!transfer->tx_buf) - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, + STM32H7_SPI_CR1_HDDIR); else if (!transfer->rx_buf) - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, + STM32H7_SPI_CR1_HDDIR); } else { if (!transfer->tx_buf) - mode = SPI_SIMPLEX_RX; + mode = STM32H7_SPI_SIMPLEX_RX; else if (!transfer->rx_buf) - mode = SPI_SIMPLEX_TX; + mode = STM32H7_SPI_SIMPLEX_TX; } if (spi->cur_comm != mode) { spi->cur_comm = mode; - cfg2_clrb |= SPI_CFG2_COMM; - cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM; + cfg2_clrb |= STM32H7_SPI_CFG2_COMM; + cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & + STM32H7_SPI_CFG2_COMM; } - cfg2_clrb |= SPI_CFG2_MIDI; + cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; if ((transfer->len > 1) && (spi->cur_midi > 0)) { - u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); + u32 sck_period_ns = DIV_ROUND_UP(STM32H7_SPI_1HZ_NS, + spi->cur_speed); u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), - (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT); + (u32)STM32H7_SPI_CFG2_MIDI >> + STM32H7_SPI_CFG2_MIDI_SHIFT); dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", sck_period_ns, midi, midi * sck_period_ns); - cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI; + cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & + STM32H7_SPI_CFG2_MIDI; } if (cfg2_clrb || cfg2_setb) - writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) & + writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & ~cfg2_clrb) | cfg2_setb, - spi->base + STM32_SPI_CFG2); + spi->base + STM32H7_SPI_CFG2); if (spi->cur_bpw <= 8) nb_words = transfer->len; @@ -950,10 +967,10 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, nb_words = DIV_ROUND_UP(transfer->len * 8, 16); else nb_words = DIV_ROUND_UP(transfer->len * 8, 32); - nb_words <<= SPI_CR2_TSIZE_SHIFT; + nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT; - if (nb_words <= SPI_CR2_TSIZE) { - writel_relaxed(nb_words, spi->base + STM32_SPI_CR2); + if (nb_words <= STM32H7_SPI_CR2_TSIZE) { + writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2); } else { ret = -EMSGSIZE; goto out; @@ -979,16 +996,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, } /** - * stm32_spi_transfer_one - transfer a single spi_transfer + * stm32h7_spi_transfer_one - transfer a single spi_transfer * * It must return 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one(struct spi_master *master, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static int stm32h7_spi_transfer_one(struct spi_master *master, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); int ret; spi->tx_buf = transfer->tx_buf; @@ -997,58 +1014,59 @@ static int stm32_spi_transfer_one(struct spi_master *master, spi->rx_len = spi->rx_buf ? transfer->len : 0; spi->cur_usedma = (master->can_dma && - stm32_spi_can_dma(master, spi_dev, transfer)); + stm32h7_spi_can_dma(master, spi_dev, transfer)); - ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); + ret = stm32h7_spi_transfer_one_setup(spi, spi_dev, transfer); if (ret) { dev_err(spi->dev, "SPI transfer setup failed\n"); return ret; } if (spi->cur_usedma) - return stm32_spi_transfer_one_dma(spi, transfer); + return stm32h7_spi_transfer_one_dma(spi, transfer); else - return stm32_spi_transfer_one_irq(spi); + return stm32h7_spi_transfer_one_irq(spi); } /** - * stm32_spi_unprepare_msg - relax the hardware + * stm32h7_spi_unprepare_msg - relax the hardware * * Normally, if TSIZE has been configured, we should relax the hardware at the * reception of the EOT interrupt. But in case of error, EOT will not be * raised. So the subsystem unprepare_message call allows us to properly * complete the transfer from an hardware point of view. */ -static int stm32_spi_unprepare_msg(struct spi_master *master, - struct spi_message *msg) +static int stm32h7_spi_unprepare_msg(struct spi_master *master, + struct spi_message *msg) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); return 0; } /** - * stm32_spi_config - Configure SPI controller as SPI master + * stm32h7_spi_config - Configure SPI controller as SPI master */ -static int stm32_spi_config(struct stm32_spi *spi) +static int stm32h7_spi_config(struct stm32h7_spi *spi) { unsigned long flags; spin_lock_irqsave(&spi->lock, flags); /* Ensure I2SMOD bit is kept cleared */ - stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, + STM32H7_SPI_I2SCFGR_I2SMOD); /* * - SS input value high * - transmitter half duplex direction * - automatic communication suspend when RX-Fifo is full */ - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI | - SPI_CR1_HDDIR | - SPI_CR1_MASRX); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | + STM32H7_SPI_CR1_HDDIR | + STM32H7_SPI_CR1_MASRX); /* * - Set the master mode (default Motorola mode) @@ -1056,29 +1074,29 @@ static int stm32_spi_config(struct stm32_spi *spi) * SS input value is determined by the SSI bit * - keep control of all associated GPIOs */ - stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER | - SPI_CFG2_SSM | - SPI_CFG2_AFCNTR); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | + STM32H7_SPI_CFG2_SSM | + STM32H7_SPI_CFG2_AFCNTR); spin_unlock_irqrestore(&spi->lock, flags); return 0; } -static const struct of_device_id stm32_spi_of_match[] = { +static const struct of_device_id stm32h7_spi_of_match[] = { { .compatible = "st,stm32h7-spi", }, {}, }; -MODULE_DEVICE_TABLE(of, stm32_spi_of_match); +MODULE_DEVICE_TABLE(of, stm32h7_spi_of_match); -static int stm32_spi_probe(struct platform_device *pdev) +static int stm32h7_spi_probe(struct platform_device *pdev) { struct spi_master *master; - struct stm32_spi *spi; + struct stm32h7_spi *spi; struct resource *res; int i, ret; - master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); + master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi)); if (!master) { dev_err(&pdev->dev, "spi master allocation failed\n"); return -ENOMEM; @@ -1105,7 +1123,7 @@ static int stm32_spi_probe(struct platform_device *pdev) goto err_master_put; } ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL, - stm32_spi_irq, IRQF_ONESHOT, + stm32h7_spi_irq, IRQF_ONESHOT, pdev->name, master); if (ret) { dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, @@ -1139,9 +1157,9 @@ static int stm32_spi_probe(struct platform_device *pdev) reset_control_deassert(spi->rst); } - spi->fifo_size = stm32_spi_get_fifo_size(spi); + spi->fifo_size = stm32h7_spi_get_fifo_size(spi); - ret = stm32_spi_config(spi); + ret = stm32h7_spi_config(spi); if (ret) { dev_err(&pdev->dev, "controller configuration failed: %d\n", ret); @@ -1153,13 +1171,13 @@ static int stm32_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP; - master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi); - master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN; - master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX; - master->setup = stm32_spi_setup; - master->prepare_message = stm32_spi_prepare_msg; - master->transfer_one = stm32_spi_transfer_one; - master->unprepare_message = stm32_spi_unprepare_msg; + master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi); + master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN; + master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX; + master->setup = stm32h7_spi_setup; + master->prepare_message = stm32h7_spi_prepare_msg; + master->transfer_one = stm32h7_spi_transfer_one; + master->unprepare_message = stm32h7_spi_unprepare_msg; spi->dma_tx = dma_request_slave_channel(spi->dev, "tx"); if (!spi->dma_tx) @@ -1174,7 +1192,7 @@ static int stm32_spi_probe(struct platform_device *pdev) master->dma_rx = spi->dma_rx; if (spi->dma_tx || spi->dma_rx) - master->can_dma = stm32_spi_can_dma; + master->can_dma = stm32h7_spi_can_dma; pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); @@ -1228,12 +1246,12 @@ static int stm32_spi_probe(struct platform_device *pdev) return ret; } -static int stm32_spi_remove(struct platform_device *pdev) +static int stm32h7_spi_remove(struct platform_device *pdev) { struct spi_master *master = platform_get_drvdata(pdev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); if (master->dma_tx) dma_release_channel(master->dma_tx); @@ -1248,27 +1266,27 @@ static int stm32_spi_remove(struct platform_device *pdev) } #ifdef CONFIG_PM -static int stm32_spi_runtime_suspend(struct device *dev) +static int stm32h7_spi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); clk_disable_unprepare(spi->clk); return 0; } -static int stm32_spi_runtime_resume(struct device *dev) +static int stm32h7_spi_runtime_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); return clk_prepare_enable(spi->clk); } #endif #ifdef CONFIG_PM_SLEEP -static int stm32_spi_suspend(struct device *dev) +static int stm32h7_spi_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); int ret; @@ -1280,10 +1298,10 @@ static int stm32_spi_suspend(struct device *dev) return pm_runtime_force_suspend(dev); } -static int stm32_spi_resume(struct device *dev) +static int stm32h7_spi_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); int ret; ret = pm_runtime_force_resume(dev); @@ -1298,23 +1316,23 @@ static int stm32_spi_resume(struct device *dev) } #endif -static const struct dev_pm_ops stm32_spi_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) - SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, - stm32_spi_runtime_resume, NULL) +static const struct dev_pm_ops stm32h7_spi_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(stm32h7_spi_suspend, stm32h7_spi_resume) + SET_RUNTIME_PM_OPS(stm32h7_spi_runtime_suspend, + stm32h7_spi_runtime_resume, NULL) }; -static struct platform_driver stm32_spi_driver = { - .probe = stm32_spi_probe, - .remove = stm32_spi_remove, +static struct platform_driver stm32h7_spi_driver = { + .probe = stm32h7_spi_probe, + .remove = stm32h7_spi_remove, .driver = { .name = DRIVER_NAME, - .pm = &stm32_spi_pm_ops, - .of_match_table = stm32_spi_of_match, + .pm = &stm32h7_spi_pm_ops, + .of_match_table = stm32h7_spi_of_match, }, }; -module_platform_driver(stm32_spi_driver); +module_platform_driver(stm32h7_spi_driver); MODULE_ALIAS("platform:" DRIVER_NAME); MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: cezary.gapinski@gmail.com To: Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Amelie Delaunay <amelie.delaunay@st.com>, Cezary Gapinski <cezary.gapinski@gmail.com>, Alexandre Torgue <alexandre.torgue@st.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com> Subject: [PATCH 1/5] spi: stm32: rename STM32 SPI registers and functions to STM32H7 Date: Sun, 9 Dec 2018 14:53:52 +0100 [thread overview] Message-ID: <1544363636-12161-2-git-send-email-cezary.gapinski@gmail.com> (raw) In-Reply-To: <1544363636-12161-1-git-send-email-cezary.gapinski@gmail.com> From: Cezary Gapinski <cezary.gapinski@gmail.com> Rename STM32 SPI registers and functions to be related to STM32H7 SPI driver and not STM32 generally. Signed-off-by: Cezary Gapinski <cezary.gapinski@gmail.com> --- drivers/spi/spi-stm32.c | 662 +++++++++++++++++++++++++----------------------- 1 file changed, 340 insertions(+), 322 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index ad1e55d..eb4d93e 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -33,97 +33,97 @@ #define DRIVER_NAME "spi_stm32" -/* STM32 SPI registers */ -#define STM32_SPI_CR1 0x00 -#define STM32_SPI_CR2 0x04 -#define STM32_SPI_CFG1 0x08 -#define STM32_SPI_CFG2 0x0C -#define STM32_SPI_IER 0x10 -#define STM32_SPI_SR 0x14 -#define STM32_SPI_IFCR 0x18 -#define STM32_SPI_TXDR 0x20 -#define STM32_SPI_RXDR 0x30 -#define STM32_SPI_I2SCFGR 0x50 - -/* STM32_SPI_CR1 bit fields */ -#define SPI_CR1_SPE BIT(0) -#define SPI_CR1_MASRX BIT(8) -#define SPI_CR1_CSTART BIT(9) -#define SPI_CR1_CSUSP BIT(10) -#define SPI_CR1_HDDIR BIT(11) -#define SPI_CR1_SSI BIT(12) - -/* STM32_SPI_CR2 bit fields */ -#define SPI_CR2_TSIZE_SHIFT 0 -#define SPI_CR2_TSIZE GENMASK(15, 0) - -/* STM32_SPI_CFG1 bit fields */ -#define SPI_CFG1_DSIZE_SHIFT 0 -#define SPI_CFG1_DSIZE GENMASK(4, 0) -#define SPI_CFG1_FTHLV_SHIFT 5 -#define SPI_CFG1_FTHLV GENMASK(8, 5) -#define SPI_CFG1_RXDMAEN BIT(14) -#define SPI_CFG1_TXDMAEN BIT(15) -#define SPI_CFG1_MBR_SHIFT 28 -#define SPI_CFG1_MBR GENMASK(30, 28) -#define SPI_CFG1_MBR_MIN 0 -#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) - -/* STM32_SPI_CFG2 bit fields */ -#define SPI_CFG2_MIDI_SHIFT 4 -#define SPI_CFG2_MIDI GENMASK(7, 4) -#define SPI_CFG2_COMM_SHIFT 17 -#define SPI_CFG2_COMM GENMASK(18, 17) -#define SPI_CFG2_SP_SHIFT 19 -#define SPI_CFG2_SP GENMASK(21, 19) -#define SPI_CFG2_MASTER BIT(22) -#define SPI_CFG2_LSBFRST BIT(23) -#define SPI_CFG2_CPHA BIT(24) -#define SPI_CFG2_CPOL BIT(25) -#define SPI_CFG2_SSM BIT(26) -#define SPI_CFG2_AFCNTR BIT(31) - -/* STM32_SPI_IER bit fields */ -#define SPI_IER_RXPIE BIT(0) -#define SPI_IER_TXPIE BIT(1) -#define SPI_IER_DXPIE BIT(2) -#define SPI_IER_EOTIE BIT(3) -#define SPI_IER_TXTFIE BIT(4) -#define SPI_IER_OVRIE BIT(6) -#define SPI_IER_MODFIE BIT(9) -#define SPI_IER_ALL GENMASK(10, 0) - -/* STM32_SPI_SR bit fields */ -#define SPI_SR_RXP BIT(0) -#define SPI_SR_TXP BIT(1) -#define SPI_SR_EOT BIT(3) -#define SPI_SR_OVR BIT(6) -#define SPI_SR_MODF BIT(9) -#define SPI_SR_SUSP BIT(11) -#define SPI_SR_RXPLVL_SHIFT 13 -#define SPI_SR_RXPLVL GENMASK(14, 13) -#define SPI_SR_RXWNE BIT(15) - -/* STM32_SPI_IFCR bit fields */ -#define SPI_IFCR_ALL GENMASK(11, 3) - -/* STM32_SPI_I2SCFGR bit fields */ -#define SPI_I2SCFGR_I2SMOD BIT(0) - -/* SPI Master Baud Rate min/max divisor */ -#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN) -#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX) - -/* SPI Communication mode */ -#define SPI_FULL_DUPLEX 0 -#define SPI_SIMPLEX_TX 1 -#define SPI_SIMPLEX_RX 2 -#define SPI_HALF_DUPLEX 3 - -#define SPI_1HZ_NS 1000000000 +/* STM32H7 SPI registers */ +#define STM32H7_SPI_CR1 0x00 +#define STM32H7_SPI_CR2 0x04 +#define STM32H7_SPI_CFG1 0x08 +#define STM32H7_SPI_CFG2 0x0C +#define STM32H7_SPI_IER 0x10 +#define STM32H7_SPI_SR 0x14 +#define STM32H7_SPI_IFCR 0x18 +#define STM32H7_SPI_TXDR 0x20 +#define STM32H7_SPI_RXDR 0x30 +#define STM32H7_SPI_I2SCFGR 0x50 + +/* STM32H7_SPI_CR1 bit fields */ +#define STM32H7_SPI_CR1_SPE BIT(0) +#define STM32H7_SPI_CR1_MASRX BIT(8) +#define STM32H7_SPI_CR1_CSTART BIT(9) +#define STM32H7_SPI_CR1_CSUSP BIT(10) +#define STM32H7_SPI_CR1_HDDIR BIT(11) +#define STM32H7_SPI_CR1_SSI BIT(12) + +/* STM32H7_SPI_CR2 bit fields */ +#define STM32H7_SPI_CR2_TSIZE_SHIFT 0 +#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) + +/* STM32H7_SPI_CFG1 bit fields */ +#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 +#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) +#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 +#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) +#define STM32H7_SPI_CFG1_RXDMAEN BIT(14) +#define STM32H7_SPI_CFG1_TXDMAEN BIT(15) +#define STM32H7_SPI_CFG1_MBR_SHIFT 28 +#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) +#define STM32H7_SPI_CFG1_MBR_MIN 0 +#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) + +/* STM32H7_SPI_CFG2 bit fields */ +#define STM32H7_SPI_CFG2_MIDI_SHIFT 4 +#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) +#define STM32H7_SPI_CFG2_COMM_SHIFT 17 +#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) +#define STM32H7_SPI_CFG2_SP_SHIFT 19 +#define STM32H7_SPI_CFG2_SP GENMASK(21, 19) +#define STM32H7_SPI_CFG2_MASTER BIT(22) +#define STM32H7_SPI_CFG2_LSBFRST BIT(23) +#define STM32H7_SPI_CFG2_CPHA BIT(24) +#define STM32H7_SPI_CFG2_CPOL BIT(25) +#define STM32H7_SPI_CFG2_SSM BIT(26) +#define STM32H7_SPI_CFG2_AFCNTR BIT(31) + +/* STM32H7_SPI_IER bit fields */ +#define STM32H7_SPI_IER_RXPIE BIT(0) +#define STM32H7_SPI_IER_TXPIE BIT(1) +#define STM32H7_SPI_IER_DXPIE BIT(2) +#define STM32H7_SPI_IER_EOTIE BIT(3) +#define STM32H7_SPI_IER_TXTFIE BIT(4) +#define STM32H7_SPI_IER_OVRIE BIT(6) +#define STM32H7_SPI_IER_MODFIE BIT(9) +#define STM32H7_SPI_IER_ALL GENMASK(10, 0) + +/* STM32H7_SPI_SR bit fields */ +#define STM32H7_SPI_SR_RXP BIT(0) +#define STM32H7_SPI_SR_TXP BIT(1) +#define STM32H7_SPI_SR_EOT BIT(3) +#define STM32H7_SPI_SR_OVR BIT(6) +#define STM32H7_SPI_SR_MODF BIT(9) +#define STM32H7_SPI_SR_SUSP BIT(11) +#define STM32H7_SPI_SR_RXPLVL_SHIFT 13 +#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) +#define STM32H7_SPI_SR_RXWNE BIT(15) + +/* STM32H7_SPI_IFCR bit fields */ +#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) + +/* STM32H7_SPI_I2SCFGR bit fields */ +#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) + +/* STM32H7 SPI Master Baud Rate min/max divisor */ +#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) +#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) + +/* STM32H7 SPI Communication mode */ +#define STM32H7_SPI_FULL_DUPLEX 0 +#define STM32H7_SPI_SIMPLEX_TX 1 +#define STM32H7_SPI_SIMPLEX_RX 2 +#define STM32H7_SPI_HALF_DUPLEX 3 + +#define STM32H7_SPI_1HZ_NS 1000000000 /** - * struct stm32_spi - private data of the SPI controller + * struct stm32h7_spi - private data of the SPI controller * @dev: driver model representation of the controller * @master: controller master interface * @base: virtual memory area @@ -148,7 +148,7 @@ * @dma_rx: dma channel for RX transfer * @phys_addr: SPI registers physical base address */ -struct stm32_spi { +struct stm32h7_spi { struct device *dev; struct spi_master *master; void __iomem *base; @@ -176,37 +176,37 @@ struct stm32_spi { dma_addr_t phys_addr; }; -static inline void stm32_spi_set_bits(struct stm32_spi *spi, - u32 offset, u32 bits) +static inline void stm32h7_spi_set_bits(struct stm32h7_spi *spi, + u32 offset, u32 bits) { writel_relaxed(readl_relaxed(spi->base + offset) | bits, spi->base + offset); } -static inline void stm32_spi_clr_bits(struct stm32_spi *spi, - u32 offset, u32 bits) +static inline void stm32h7_spi_clr_bits(struct stm32h7_spi *spi, + u32 offset, u32 bits) { writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, spi->base + offset); } /** - * stm32_spi_get_fifo_size - Return fifo size + * stm32h7_spi_get_fifo_size - Return fifo size * @spi: pointer to the spi controller data structure */ -static int stm32_spi_get_fifo_size(struct stm32_spi *spi) +static int stm32h7_spi_get_fifo_size(struct stm32h7_spi *spi) { unsigned long flags; u32 count = 0; spin_lock_irqsave(&spi->lock, flags); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); - while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP) - writeb_relaxed(++count, spi->base + STM32_SPI_TXDR); + while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) + writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); spin_unlock_irqrestore(&spi->lock, flags); @@ -216,10 +216,10 @@ static int stm32_spi_get_fifo_size(struct stm32_spi *spi) } /** - * stm32_spi_get_bpw_mask - Return bits per word mask + * stm32h7_spi_get_bpw_mask - Return bits per word mask * @spi: pointer to the spi controller data structure */ -static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) +static int stm32h7_spi_get_bpw_mask(struct stm32h7_spi *spi) { unsigned long flags; u32 cfg1, max_bpw; @@ -230,10 +230,11 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) * The most significant bit at DSIZE bit field is reserved when the * maximum data size of periperal instances is limited to 16-bit */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); - cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1); - max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT; + cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); + max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> + STM32H7_SPI_CFG1_DSIZE_SHIFT; max_bpw += 1; spin_unlock_irqrestore(&spi->lock, flags); @@ -244,13 +245,13 @@ static int stm32_spi_get_bpw_mask(struct stm32_spi *spi) } /** - * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value + * stm32h7_spi_prepare_mbr - Determine STM32H7_SPI_CFG1.MBR value * @spi: pointer to the spi controller data structure * @speed_hz: requested speed * - * Return SPI_CFG1.MBR value in case of success or -EINVAL + * Return STM32H7_SPI_CFG1.MBR value in case of success or -EINVAL */ -static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) +static int stm32h7_spi_prepare_mbr(struct stm32h7_spi *spi, u32 speed_hz) { u32 div, mbrdiv; @@ -263,8 +264,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) * no need to check it there. * However, we need to ensure the following calculations. */ - if (div < SPI_MBR_DIV_MIN || - div > SPI_MBR_DIV_MAX) + if (div < STM32H7_SPI_MBR_DIV_MIN || + div > STM32H7_SPI_MBR_DIV_MAX) return -EINVAL; /* Determine the first power of 2 greater than or equal to div */ @@ -279,10 +280,10 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz) } /** - * stm32_spi_prepare_fthlv - Determine FIFO threshold level + * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level * @spi: pointer to the spi controller data structure */ -static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi) +static u32 stm32h7_spi_prepare_fthlv(struct stm32h7_spi *spi) { u32 fthlv, half_fifo; @@ -306,32 +307,33 @@ static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi) } /** - * stm32_spi_write_txfifo - Write bytes in Transmit Data Register + * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register * @spi: pointer to the spi controller data structure * * Read from tx_buf depends on remaining bytes to avoid to read beyond * tx_buf end. */ -static void stm32_spi_write_txfifo(struct stm32_spi *spi) +static void stm32h7_spi_write_txfifo(struct stm32h7_spi *spi) { while ((spi->tx_len > 0) && - (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) { + (readl_relaxed(spi->base + STM32H7_SPI_SR) & + STM32H7_SPI_SR_TXP)) { u32 offs = spi->cur_xferlen - spi->tx_len; if (spi->tx_len >= sizeof(u32)) { const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); - writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR); + writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u32); } else if (spi->tx_len >= sizeof(u16)) { const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); - writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR); + writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u16); } else { const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); - writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR); + writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); spi->tx_len -= sizeof(u8); } } @@ -340,43 +342,45 @@ static void stm32_spi_write_txfifo(struct stm32_spi *spi) } /** - * stm32_spi_read_rxfifo - Read bytes in Receive Data Register + * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register * @spi: pointer to the spi controller data structure * * Write in rx_buf depends on remaining bytes to avoid to write beyond * rx_buf end. */ -static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush) +static void stm32h7_spi_read_rxfifo(struct stm32h7_spi *spi, bool flush) { - u32 sr = readl_relaxed(spi->base + STM32_SPI_SR); - u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> + STM32H7_SPI_SR_RXPLVL_SHIFT; while ((spi->rx_len > 0) && - ((sr & SPI_SR_RXP) || - (flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) { + ((sr & STM32H7_SPI_SR_RXP) || + (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { u32 offs = spi->cur_xferlen - spi->rx_len; if ((spi->rx_len >= sizeof(u32)) || - (flush && (sr & SPI_SR_RXWNE))) { + (flush && (sr & STM32H7_SPI_SR_RXWNE))) { u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); - *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u32); } else if ((spi->rx_len >= sizeof(u16)) || (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); - *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u16); } else { u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); - *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR); + *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); spi->rx_len -= sizeof(u8); } - sr = readl_relaxed(spi->base + STM32_SPI_SR); - rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> + STM32H7_SPI_SR_RXPLVL_SHIFT; } dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, @@ -384,28 +388,28 @@ static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush) } /** - * stm32_spi_enable - Enable SPI controller + * stm32h7_spi_enable - Enable SPI controller * @spi: pointer to the spi controller data structure * * SPI data transfer is enabled but spi_ker_ck is idle. - * SPI_CFG1 and SPI_CFG2 are now write protected. + * STM32H7_SPI_CFG1 and STM32H7_SPI_CFG2 are now write protected. */ -static void stm32_spi_enable(struct stm32_spi *spi) +static void stm32h7_spi_enable(struct stm32h7_spi *spi) { dev_dbg(spi->dev, "enable controller\n"); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); } /** - * stm32_spi_disable - Disable SPI controller + * stm32h7_spi_disable - Disable SPI controller * @spi: pointer to the spi controller data structure * * RX-Fifo is flushed when SPI controller is disabled. To prevent any data - * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in + * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in * RX-Fifo. */ -static void stm32_spi_disable(struct stm32_spi *spi) +static void stm32h7_spi_disable(struct stm32h7_spi *spi) { unsigned long flags; u32 cr1, sr; @@ -414,23 +418,23 @@ static void stm32_spi_disable(struct stm32_spi *spi) spin_lock_irqsave(&spi->lock, flags); - cr1 = readl_relaxed(spi->base + STM32_SPI_CR1); + cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); - if (!(cr1 & SPI_CR1_SPE)) { + if (!(cr1 & STM32H7_SPI_CR1_SPE)) { spin_unlock_irqrestore(&spi->lock, flags); return; } /* Wait on EOT or suspend the flow */ - if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR, - sr, !(sr & SPI_SR_EOT), + if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, + sr, !(sr & STM32H7_SPI_SR_EOT), 10, 100000) < 0) { - if (cr1 & SPI_CR1_CSTART) { - writel_relaxed(cr1 | SPI_CR1_CSUSP, - spi->base + STM32_SPI_CR1); + if (cr1 & STM32H7_SPI_CR1_CSTART) { + writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, + spi->base + STM32H7_SPI_CR1); if (readl_relaxed_poll_timeout_atomic( - spi->base + STM32_SPI_SR, - sr, !(sr & SPI_SR_SUSP), + spi->base + STM32H7_SPI_SR, + sr, !(sr & STM32H7_SPI_SR_SUSP), 10, 100000) < 0) dev_warn(spi->dev, "Suspend request timeout\n"); @@ -438,35 +442,35 @@ static void stm32_spi_disable(struct stm32_spi *spi) } if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) - stm32_spi_read_rxfifo(spi, true); + stm32h7_spi_read_rxfifo(spi, true); if (spi->cur_usedma && spi->tx_buf) dmaengine_terminate_all(spi->dma_tx); if (spi->cur_usedma && spi->rx_buf) dmaengine_terminate_all(spi->dma_rx); - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); - stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN | - SPI_CFG1_RXDMAEN); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | + STM32H7_SPI_CFG1_RXDMAEN); /* Disable interrupts and clear status flags */ - writel_relaxed(0, spi->base + STM32_SPI_IER); - writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR); + writel_relaxed(0, spi->base + STM32H7_SPI_IER); + writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); spin_unlock_irqrestore(&spi->lock, flags); } /** - * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use + * stm32h7_spi_can_dma - Determine if the transfer is eligible for DMA use * * If the current transfer size is greater than fifo size, use DMA. */ -static bool stm32_spi_can_dma(struct spi_master *master, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static bool stm32h7_spi_can_dma(struct spi_master *master, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); dev_dbg(spi->dev, "%s: %s\n", __func__, (transfer->len > spi->fifo_size) ? "true" : "false"); @@ -475,33 +479,33 @@ static bool stm32_spi_can_dma(struct spi_master *master, } /** - * stm32_spi_irq - Interrupt handler for SPI controller events + * stm32h7_spi_irq - Interrupt handler for SPI controller events * @irq: interrupt line * @dev_id: SPI controller master interface */ -static irqreturn_t stm32_spi_irq(int irq, void *dev_id) +static irqreturn_t stm32h7_spi_irq(int irq, void *dev_id) { struct spi_master *master = dev_id; - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); u32 sr, ier, mask; unsigned long flags; bool end = false; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32_SPI_SR); - ier = readl_relaxed(spi->base + STM32_SPI_IER); + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + ier = readl_relaxed(spi->base + STM32H7_SPI_IER); mask = ier; /* EOTIE is triggered on EOT, SUSP and TXC events. */ - mask |= SPI_SR_SUSP; + mask |= STM32H7_SPI_SR_SUSP; /* * When TXTF is set, DXPIE and TXPIE are cleared. So in case of * Full-Duplex, need to poll RXP event to know if there are remaining * data, before disabling SPI. */ if (spi->rx_buf && !spi->cur_usedma) - mask |= SPI_SR_RXP; + mask |= STM32H7_SPI_SR_RXP; if (!(sr & mask)) { dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", @@ -510,10 +514,10 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) return IRQ_NONE; } - if (sr & SPI_SR_SUSP) { + if (sr & STM32H7_SPI_SR_SUSP) { dev_warn(spi->dev, "Communication suspended\n"); if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); /* * If communication is suspended while using DMA, it means * that something went wrong, so stop the current transfer @@ -522,15 +526,15 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) end = true; } - if (sr & SPI_SR_MODF) { + if (sr & STM32H7_SPI_SR_MODF) { dev_warn(spi->dev, "Mode fault: transfer aborted\n"); end = true; } - if (sr & SPI_SR_OVR) { + if (sr & STM32H7_SPI_SR_OVR) { dev_warn(spi->dev, "Overrun: received value discarded\n"); if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); /* * If overrun is detected while using DMA, it means that * something went wrong, so stop the current transfer @@ -539,36 +543,36 @@ static irqreturn_t stm32_spi_irq(int irq, void *dev_id) end = true; } - if (sr & SPI_SR_EOT) { + if (sr & STM32H7_SPI_SR_EOT) { if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, true); + stm32h7_spi_read_rxfifo(spi, true); end = true; } - if (sr & SPI_SR_TXP) + if (sr & STM32H7_SPI_SR_TXP) if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) - stm32_spi_write_txfifo(spi); + stm32h7_spi_write_txfifo(spi); - if (sr & SPI_SR_RXP) + if (sr & STM32H7_SPI_SR_RXP) if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) - stm32_spi_read_rxfifo(spi, false); + stm32h7_spi_read_rxfifo(spi, false); - writel_relaxed(mask, spi->base + STM32_SPI_IFCR); + writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); spin_unlock_irqrestore(&spi->lock, flags); if (end) { spi_finalize_current_transfer(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); } return IRQ_HANDLED; } /** - * stm32_spi_setup - setup device chip select + * stm32h7_spi_setup - setup device chip select */ -static int stm32_spi_setup(struct spi_device *spi_dev) +static int stm32h7_spi_setup(struct spi_device *spi_dev) { int ret = 0; @@ -589,12 +593,12 @@ static int stm32_spi_setup(struct spi_device *spi_dev) } /** - * stm32_spi_prepare_msg - set up the controller to transfer a single message + * stm32h7_spi_prepare_msg - set up the controller to transfer a single message */ -static int stm32_spi_prepare_msg(struct spi_master *master, - struct spi_message *msg) +static int stm32h7_spi_prepare_msg(struct spi_master *master, + struct spi_message *msg) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); struct spi_device *spi_dev = msg->spi; struct device_node *np = spi_dev->dev.of_node; unsigned long flags; @@ -606,19 +610,19 @@ static int stm32_spi_prepare_msg(struct spi_master *master, dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); if (spi_dev->mode & SPI_CPOL) - cfg2_setb |= SPI_CFG2_CPOL; + cfg2_setb |= STM32H7_SPI_CFG2_CPOL; else - cfg2_clrb |= SPI_CFG2_CPOL; + cfg2_clrb |= STM32H7_SPI_CFG2_CPOL; if (spi_dev->mode & SPI_CPHA) - cfg2_setb |= SPI_CFG2_CPHA; + cfg2_setb |= STM32H7_SPI_CFG2_CPHA; else - cfg2_clrb |= SPI_CFG2_CPHA; + cfg2_clrb |= STM32H7_SPI_CFG2_CPHA; if (spi_dev->mode & SPI_LSB_FIRST) - cfg2_setb |= SPI_CFG2_LSBFRST; + cfg2_setb |= STM32H7_SPI_CFG2_LSBFRST; else - cfg2_clrb |= SPI_CFG2_LSBFRST; + cfg2_clrb |= STM32H7_SPI_CFG2_LSBFRST; dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", spi_dev->mode & SPI_CPOL, @@ -630,9 +634,9 @@ static int stm32_spi_prepare_msg(struct spi_master *master, if (cfg2_clrb || cfg2_setb) writel_relaxed( - (readl_relaxed(spi->base + STM32_SPI_CFG2) & + (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & ~cfg2_clrb) | cfg2_setb, - spi->base + STM32_SPI_CFG2); + spi->base + STM32H7_SPI_CFG2); spin_unlock_irqrestore(&spi->lock, flags); @@ -640,36 +644,36 @@ static int stm32_spi_prepare_msg(struct spi_master *master, } /** - * stm32_spi_dma_cb - dma callback + * stm32h7_spi_dma_cb - dma callback * * DMA callback is called when the transfer is complete or when an error * occurs. If the transfer is complete, EOT flag is raised. */ -static void stm32_spi_dma_cb(void *data) +static void stm32h7_spi_dma_cb(void *data) { - struct stm32_spi *spi = data; + struct stm32h7_spi *spi = data; unsigned long flags; u32 sr; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32_SPI_SR); + sr = readl_relaxed(spi->base + STM32H7_SPI_SR); spin_unlock_irqrestore(&spi->lock, flags); - if (!(sr & SPI_SR_EOT)) + if (!(sr & STM32H7_SPI_SR_EOT)) dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); /* Now wait for EOT, or SUSP or OVR in case of error */ } /** - * stm32_spi_dma_config - configure dma slave channel depending on current - * transfer bits_per_word. + * stm32h7_spi_dma_config - configure dma slave channel depending on current + * transfer bits_per_word. */ -static void stm32_spi_dma_config(struct stm32_spi *spi, - struct dma_slave_config *dma_conf, - enum dma_transfer_direction dir) +static void stm32h7_spi_dma_config(struct stm32h7_spi *spi, + struct dma_slave_config *dma_conf, + enum dma_transfer_direction dir) { enum dma_slave_buswidth buswidth; u32 maxburst; @@ -690,14 +694,14 @@ static void stm32_spi_dma_config(struct stm32_spi *spi, memset(dma_conf, 0, sizeof(struct dma_slave_config)); dma_conf->direction = dir; if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ - dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR; + dma_conf->src_addr = spi->phys_addr + STM32H7_SPI_RXDR; dma_conf->src_addr_width = buswidth; dma_conf->src_maxburst = maxburst; dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", buswidth, maxburst); } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ - dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR; + dma_conf->dst_addr = spi->phys_addr + STM32H7_SPI_TXDR; dma_conf->dst_addr_width = buswidth; dma_conf->dst_maxburst = maxburst; @@ -707,39 +711,40 @@ static void stm32_spi_dma_config(struct stm32_spi *spi, } /** - * stm32_spi_transfer_one_irq - transfer a single spi_transfer using - * interrupts + * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using + * interrupts * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one_irq(struct stm32_spi *spi) +static int stm32h7_spi_transfer_one_irq(struct stm32h7_spi *spi) { unsigned long flags; u32 ier = 0; /* Enable the interrupts relative to the current communication mode */ if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ - ier |= SPI_IER_DXPIE; + ier |= STM32H7_SPI_IER_DXPIE; else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ - ier |= SPI_IER_TXPIE; + ier |= STM32H7_SPI_IER_TXPIE; else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ - ier |= SPI_IER_RXPIE; + ier |= STM32H7_SPI_IER_RXPIE; /* Enable the interrupts relative to the end of transfer */ - ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE; + ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | + STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; spin_lock_irqsave(&spi->lock, flags); - stm32_spi_enable(spi); + stm32h7_spi_enable(spi); /* Be sure to have data in fifo before starting data transfer */ if (spi->tx_buf) - stm32_spi_write_txfifo(spi); + stm32h7_spi_write_txfifo(spi); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); - writel_relaxed(ier, spi->base + STM32_SPI_IER); + writel_relaxed(ier, spi->base + STM32H7_SPI_IER); spin_unlock_irqrestore(&spi->lock, flags); @@ -747,13 +752,13 @@ static int stm32_spi_transfer_one_irq(struct stm32_spi *spi) } /** - * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA + * stm32h7_spi_transfer_one_dma - transfer a single spi_transfer using DMA * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, - struct spi_transfer *xfer) +static int stm32h7_spi_transfer_one_dma(struct stm32h7_spi *spi, + struct spi_transfer *xfer) { struct dma_slave_config tx_dma_conf, rx_dma_conf; struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; @@ -764,11 +769,12 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, rx_dma_desc = NULL; if (spi->rx_buf) { - stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); + stm32h7_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); /* Enable Rx DMA request */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, + STM32H7_SPI_CFG1_RXDMAEN); rx_dma_desc = dmaengine_prep_slave_sg( spi->dma_rx, xfer->rx_sg.sgl, @@ -779,7 +785,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, tx_dma_desc = NULL; if (spi->tx_buf) { - stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); + stm32h7_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); tx_dma_desc = dmaengine_prep_slave_sg( @@ -794,7 +800,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, goto dma_desc_error; if (rx_dma_desc) { - rx_dma_desc->callback = stm32_spi_dma_cb; + rx_dma_desc->callback = stm32h7_spi_dma_cb; rx_dma_desc->callback_param = spi; if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { @@ -806,8 +812,8 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, } if (tx_dma_desc) { - if (spi->cur_comm == SPI_SIMPLEX_TX) { - tx_dma_desc->callback = stm32_spi_dma_cb; + if (spi->cur_comm == STM32H7_SPI_SIMPLEX_TX) { + tx_dma_desc->callback = stm32h7_spi_dma_cb; tx_dma_desc->callback_param = spi; } @@ -819,16 +825,18 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, dma_async_issue_pending(spi->dma_tx); /* Enable Tx DMA request */ - stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG1, + STM32H7_SPI_CFG1_TXDMAEN); } /* Enable the interrupts relative to the end of transfer */ - ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE; - writel_relaxed(ier, spi->base + STM32_SPI_IER); + ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | + STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; + writel_relaxed(ier, spi->base + STM32H7_SPI_IER); - stm32_spi_enable(spi); + stm32h7_spi_enable(spi); - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); spin_unlock_irqrestore(&spi->lock, flags); @@ -839,23 +847,23 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, dmaengine_terminate_all(spi->dma_rx); dma_desc_error: - stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN); spin_unlock_irqrestore(&spi->lock, flags); dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); - return stm32_spi_transfer_one_irq(spi); + return stm32h7_spi_transfer_one_irq(spi); } /** - * stm32_spi_transfer_one_setup - common setup to transfer a single - * spi_transfer either using DMA or - * interrupts. + * stm32h7_spi_transfer_one_setup - common setup to transfer a single + * spi_transfer either using DMA or + * interrupts. */ -static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static int stm32h7_spi_transfer_one_setup(struct stm32h7_spi *spi, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { unsigned long flags; u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0; @@ -870,21 +878,23 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, spi->cur_bpw = transfer->bits_per_word; bpw = spi->cur_bpw - 1; - cfg1_clrb |= SPI_CFG1_DSIZE; - cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE; + cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; + cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & + STM32H7_SPI_CFG1_DSIZE; - spi->cur_fthlv = stm32_spi_prepare_fthlv(spi); + spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi); fthlv = spi->cur_fthlv - 1; - cfg1_clrb |= SPI_CFG1_FTHLV; - cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV; + cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; + cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & + STM32H7_SPI_CFG1_FTHLV; } if (spi->cur_speed != transfer->speed_hz) { int mbr; /* Update spi->cur_speed with real clock speed */ - mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz); + mbr = stm32h7_spi_prepare_mbr(spi, transfer->speed_hz); if (mbr < 0) { ret = mbr; goto out; @@ -892,16 +902,17 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, transfer->speed_hz = spi->cur_speed; - cfg1_clrb |= SPI_CFG1_MBR; - cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR; + cfg1_clrb |= STM32H7_SPI_CFG1_MBR; + cfg1_setb |= ((u32)mbr << STM32H7_SPI_CFG1_MBR_SHIFT) & + STM32H7_SPI_CFG1_MBR; } if (cfg1_clrb || cfg1_setb) - writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) & + writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG1) & ~cfg1_clrb) | cfg1_setb, - spi->base + STM32_SPI_CFG1); + spi->base + STM32H7_SPI_CFG1); - mode = SPI_FULL_DUPLEX; + mode = STM32H7_SPI_FULL_DUPLEX; if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ /* * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL @@ -909,40 +920,46 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, * on the valid buffer, we can determine the direction of the * transfer. */ - mode = SPI_HALF_DUPLEX; + mode = STM32H7_SPI_HALF_DUPLEX; if (!transfer->tx_buf) - stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_CR1, + STM32H7_SPI_CR1_HDDIR); else if (!transfer->rx_buf) - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, + STM32H7_SPI_CR1_HDDIR); } else { if (!transfer->tx_buf) - mode = SPI_SIMPLEX_RX; + mode = STM32H7_SPI_SIMPLEX_RX; else if (!transfer->rx_buf) - mode = SPI_SIMPLEX_TX; + mode = STM32H7_SPI_SIMPLEX_TX; } if (spi->cur_comm != mode) { spi->cur_comm = mode; - cfg2_clrb |= SPI_CFG2_COMM; - cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM; + cfg2_clrb |= STM32H7_SPI_CFG2_COMM; + cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & + STM32H7_SPI_CFG2_COMM; } - cfg2_clrb |= SPI_CFG2_MIDI; + cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; if ((transfer->len > 1) && (spi->cur_midi > 0)) { - u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); + u32 sck_period_ns = DIV_ROUND_UP(STM32H7_SPI_1HZ_NS, + spi->cur_speed); u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), - (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT); + (u32)STM32H7_SPI_CFG2_MIDI >> + STM32H7_SPI_CFG2_MIDI_SHIFT); dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", sck_period_ns, midi, midi * sck_period_ns); - cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI; + cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & + STM32H7_SPI_CFG2_MIDI; } if (cfg2_clrb || cfg2_setb) - writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) & + writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & ~cfg2_clrb) | cfg2_setb, - spi->base + STM32_SPI_CFG2); + spi->base + STM32H7_SPI_CFG2); if (spi->cur_bpw <= 8) nb_words = transfer->len; @@ -950,10 +967,10 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, nb_words = DIV_ROUND_UP(transfer->len * 8, 16); else nb_words = DIV_ROUND_UP(transfer->len * 8, 32); - nb_words <<= SPI_CR2_TSIZE_SHIFT; + nb_words <<= STM32H7_SPI_CR2_TSIZE_SHIFT; - if (nb_words <= SPI_CR2_TSIZE) { - writel_relaxed(nb_words, spi->base + STM32_SPI_CR2); + if (nb_words <= STM32H7_SPI_CR2_TSIZE) { + writel_relaxed(nb_words, spi->base + STM32H7_SPI_CR2); } else { ret = -EMSGSIZE; goto out; @@ -979,16 +996,16 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, } /** - * stm32_spi_transfer_one - transfer a single spi_transfer + * stm32h7_spi_transfer_one - transfer a single spi_transfer * * It must return 0 if the transfer is finished or 1 if the transfer is still * in progress. */ -static int stm32_spi_transfer_one(struct spi_master *master, - struct spi_device *spi_dev, - struct spi_transfer *transfer) +static int stm32h7_spi_transfer_one(struct spi_master *master, + struct spi_device *spi_dev, + struct spi_transfer *transfer) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); int ret; spi->tx_buf = transfer->tx_buf; @@ -997,58 +1014,59 @@ static int stm32_spi_transfer_one(struct spi_master *master, spi->rx_len = spi->rx_buf ? transfer->len : 0; spi->cur_usedma = (master->can_dma && - stm32_spi_can_dma(master, spi_dev, transfer)); + stm32h7_spi_can_dma(master, spi_dev, transfer)); - ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); + ret = stm32h7_spi_transfer_one_setup(spi, spi_dev, transfer); if (ret) { dev_err(spi->dev, "SPI transfer setup failed\n"); return ret; } if (spi->cur_usedma) - return stm32_spi_transfer_one_dma(spi, transfer); + return stm32h7_spi_transfer_one_dma(spi, transfer); else - return stm32_spi_transfer_one_irq(spi); + return stm32h7_spi_transfer_one_irq(spi); } /** - * stm32_spi_unprepare_msg - relax the hardware + * stm32h7_spi_unprepare_msg - relax the hardware * * Normally, if TSIZE has been configured, we should relax the hardware at the * reception of the EOT interrupt. But in case of error, EOT will not be * raised. So the subsystem unprepare_message call allows us to properly * complete the transfer from an hardware point of view. */ -static int stm32_spi_unprepare_msg(struct spi_master *master, - struct spi_message *msg) +static int stm32h7_spi_unprepare_msg(struct spi_master *master, + struct spi_message *msg) { - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); return 0; } /** - * stm32_spi_config - Configure SPI controller as SPI master + * stm32h7_spi_config - Configure SPI controller as SPI master */ -static int stm32_spi_config(struct stm32_spi *spi) +static int stm32h7_spi_config(struct stm32h7_spi *spi) { unsigned long flags; spin_lock_irqsave(&spi->lock, flags); /* Ensure I2SMOD bit is kept cleared */ - stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); + stm32h7_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, + STM32H7_SPI_I2SCFGR_I2SMOD); /* * - SS input value high * - transmitter half duplex direction * - automatic communication suspend when RX-Fifo is full */ - stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI | - SPI_CR1_HDDIR | - SPI_CR1_MASRX); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | + STM32H7_SPI_CR1_HDDIR | + STM32H7_SPI_CR1_MASRX); /* * - Set the master mode (default Motorola mode) @@ -1056,29 +1074,29 @@ static int stm32_spi_config(struct stm32_spi *spi) * SS input value is determined by the SSI bit * - keep control of all associated GPIOs */ - stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER | - SPI_CFG2_SSM | - SPI_CFG2_AFCNTR); + stm32h7_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | + STM32H7_SPI_CFG2_SSM | + STM32H7_SPI_CFG2_AFCNTR); spin_unlock_irqrestore(&spi->lock, flags); return 0; } -static const struct of_device_id stm32_spi_of_match[] = { +static const struct of_device_id stm32h7_spi_of_match[] = { { .compatible = "st,stm32h7-spi", }, {}, }; -MODULE_DEVICE_TABLE(of, stm32_spi_of_match); +MODULE_DEVICE_TABLE(of, stm32h7_spi_of_match); -static int stm32_spi_probe(struct platform_device *pdev) +static int stm32h7_spi_probe(struct platform_device *pdev) { struct spi_master *master; - struct stm32_spi *spi; + struct stm32h7_spi *spi; struct resource *res; int i, ret; - master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); + master = spi_alloc_master(&pdev->dev, sizeof(struct stm32h7_spi)); if (!master) { dev_err(&pdev->dev, "spi master allocation failed\n"); return -ENOMEM; @@ -1105,7 +1123,7 @@ static int stm32_spi_probe(struct platform_device *pdev) goto err_master_put; } ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL, - stm32_spi_irq, IRQF_ONESHOT, + stm32h7_spi_irq, IRQF_ONESHOT, pdev->name, master); if (ret) { dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, @@ -1139,9 +1157,9 @@ static int stm32_spi_probe(struct platform_device *pdev) reset_control_deassert(spi->rst); } - spi->fifo_size = stm32_spi_get_fifo_size(spi); + spi->fifo_size = stm32h7_spi_get_fifo_size(spi); - ret = stm32_spi_config(spi); + ret = stm32h7_spi_config(spi); if (ret) { dev_err(&pdev->dev, "controller configuration failed: %d\n", ret); @@ -1153,13 +1171,13 @@ static int stm32_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP; - master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi); - master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN; - master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX; - master->setup = stm32_spi_setup; - master->prepare_message = stm32_spi_prepare_msg; - master->transfer_one = stm32_spi_transfer_one; - master->unprepare_message = stm32_spi_unprepare_msg; + master->bits_per_word_mask = stm32h7_spi_get_bpw_mask(spi); + master->max_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MIN; + master->min_speed_hz = spi->clk_rate / STM32H7_SPI_MBR_DIV_MAX; + master->setup = stm32h7_spi_setup; + master->prepare_message = stm32h7_spi_prepare_msg; + master->transfer_one = stm32h7_spi_transfer_one; + master->unprepare_message = stm32h7_spi_unprepare_msg; spi->dma_tx = dma_request_slave_channel(spi->dev, "tx"); if (!spi->dma_tx) @@ -1174,7 +1192,7 @@ static int stm32_spi_probe(struct platform_device *pdev) master->dma_rx = spi->dma_rx; if (spi->dma_tx || spi->dma_rx) - master->can_dma = stm32_spi_can_dma; + master->can_dma = stm32h7_spi_can_dma; pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); @@ -1228,12 +1246,12 @@ static int stm32_spi_probe(struct platform_device *pdev) return ret; } -static int stm32_spi_remove(struct platform_device *pdev) +static int stm32h7_spi_remove(struct platform_device *pdev) { struct spi_master *master = platform_get_drvdata(pdev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); - stm32_spi_disable(spi); + stm32h7_spi_disable(spi); if (master->dma_tx) dma_release_channel(master->dma_tx); @@ -1248,27 +1266,27 @@ static int stm32_spi_remove(struct platform_device *pdev) } #ifdef CONFIG_PM -static int stm32_spi_runtime_suspend(struct device *dev) +static int stm32h7_spi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); clk_disable_unprepare(spi->clk); return 0; } -static int stm32_spi_runtime_resume(struct device *dev) +static int stm32h7_spi_runtime_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); return clk_prepare_enable(spi->clk); } #endif #ifdef CONFIG_PM_SLEEP -static int stm32_spi_suspend(struct device *dev) +static int stm32h7_spi_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); int ret; @@ -1280,10 +1298,10 @@ static int stm32_spi_suspend(struct device *dev) return pm_runtime_force_suspend(dev); } -static int stm32_spi_resume(struct device *dev) +static int stm32h7_spi_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); - struct stm32_spi *spi = spi_master_get_devdata(master); + struct stm32h7_spi *spi = spi_master_get_devdata(master); int ret; ret = pm_runtime_force_resume(dev); @@ -1298,23 +1316,23 @@ static int stm32_spi_resume(struct device *dev) } #endif -static const struct dev_pm_ops stm32_spi_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) - SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, - stm32_spi_runtime_resume, NULL) +static const struct dev_pm_ops stm32h7_spi_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(stm32h7_spi_suspend, stm32h7_spi_resume) + SET_RUNTIME_PM_OPS(stm32h7_spi_runtime_suspend, + stm32h7_spi_runtime_resume, NULL) }; -static struct platform_driver stm32_spi_driver = { - .probe = stm32_spi_probe, - .remove = stm32_spi_remove, +static struct platform_driver stm32h7_spi_driver = { + .probe = stm32h7_spi_probe, + .remove = stm32h7_spi_remove, .driver = { .name = DRIVER_NAME, - .pm = &stm32_spi_pm_ops, - .of_match_table = stm32_spi_of_match, + .pm = &stm32h7_spi_pm_ops, + .of_match_table = stm32h7_spi_of_match, }, }; -module_platform_driver(stm32_spi_driver); +module_platform_driver(stm32h7_spi_driver); MODULE_ALIAS("platform:" DRIVER_NAME); MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-12-09 13:54 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-09 13:53 [PATCH 0/5] Add support for STM32F4 SPI cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski [this message] 2018-12-09 13:53 ` [PATCH 1/5] spi: stm32: rename STM32 SPI registers and functions to STM32H7 cezary.gapinski 2018-12-09 13:53 ` [PATCH 2/5] spi: stm32: rename spi-stm32 to spi-stm32h7 cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski 2018-12-09 13:53 ` [PATCH 3/5] spi: stm32: add driver for STM32F4 controller cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski 2018-12-09 13:53 ` [PATCH 4/5] ARM: dts: stm32: add SPI support on STM32F429 SoC cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski 2019-02-04 8:23 ` Alexandre Torgue 2019-02-04 8:23 ` Alexandre Torgue 2019-02-04 8:23 ` Alexandre Torgue 2018-12-09 13:53 ` [PATCH 5/5] spi: stm32: add description about STM32F4 bindings cezary.gapinski 2018-12-09 13:53 ` cezary.gapinski 2018-12-14 22:48 ` kbuild test robot 2018-12-14 22:48 ` kbuild test robot 2018-12-20 19:49 ` Rob Herring 2018-12-20 19:49 ` Rob Herring 2018-12-20 19:49 ` Rob Herring 2018-12-10 12:37 ` [PATCH 0/5] Add support for STM32F4 SPI Amelie DELAUNAY 2018-12-10 12:37 ` Amelie DELAUNAY 2018-12-10 12:37 ` Amelie DELAUNAY 2018-12-10 19:05 ` Cezary Gapiński 2018-12-10 19:05 ` Cezary Gapiński 2018-12-10 19:05 ` Cezary Gapiński 2018-12-17 12:51 ` Amelie DELAUNAY 2018-12-17 12:51 ` Amelie DELAUNAY
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