From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: ville.syrjala@intel.com, Uma Shankar <uma.shankar@intel.com>,
maarten.lankhorst@intel.com
Subject: [v2 12/14] drm/i915: Enable infoframes on GLK+ for HDR
Date: Wed, 12 Dec 2018 02:08:20 +0530 [thread overview]
Message-ID: <1544560702-16447-13-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1544560702-16447-1-git-send-email-uma.shankar@intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_hdmi.c | 12 +++++++++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..6f44d02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4591,6 +4591,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
@@ -8015,6 +8016,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8028,6 +8030,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8052,6 +8055,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6286c4a..5c2e3c9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -123,6 +123,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -146,6 +148,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -432,7 +436,8 @@ static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
}
/*
@@ -889,7 +894,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
if (!enable) {
I915_WRITE(reg, val);
@@ -908,7 +914,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
/* Set Dynamic Range and Mastering Infoframe if supported and changed */
- if (conn_state->hdr_metadata_changed)
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
}
--
1.9.1
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next prev parent reply other threads:[~2018-12-11 20:38 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-11 20:38 [v2 00/14] Add HDR Metadata Parsing and handling in DRM layer Uma Shankar
2018-12-11 20:19 ` ✗ Fi.CI.BAT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev2) Patchwork
2018-12-11 20:38 ` [v2 01/14] drm: Add HDR source metadata property Uma Shankar
2018-12-20 17:50 ` Sharma, Shashank
2019-01-08 5:29 ` Shankar, Uma
2018-12-11 20:38 ` [v2 02/14] drm: Add CEA extended tag blocks and HDR bitfield macros Uma Shankar
2018-12-20 18:07 ` Sharma, Shashank
2019-01-08 5:35 ` Shankar, Uma
2018-12-11 20:38 ` [v2 03/14] drm: Parse HDR metadata info from EDID Uma Shankar
2018-12-20 18:17 ` Sharma, Shashank
2019-01-08 5:40 ` Shankar, Uma
2019-01-08 5:56 ` Sharma, Shashank
2019-01-08 5:59 ` Shankar, Uma
2018-12-11 20:38 ` [v2 04/14] drm: Parse Colorimetry data block " Uma Shankar
2018-12-20 18:23 ` Sharma, Shashank
2019-01-08 6:40 ` Shankar, Uma
2019-01-08 6:56 ` Sharma, Shashank
2019-01-08 7:12 ` Shankar, Uma
2018-12-11 20:38 ` [v2 05/14] drm/i915: Attach HDR metadata property to connector Uma Shankar
2018-12-20 18:25 ` Sharma, Shashank
2019-01-08 6:42 ` Shankar, Uma
2018-12-11 20:38 ` [v2 06/14] drm: Add HDR capability field to plane structure Uma Shankar
2018-12-11 20:38 ` [v2 07/14] drm: Implement HDR source metadata set and get property handling Uma Shankar
2018-12-20 18:33 ` Sharma, Shashank
2019-01-08 6:48 ` Shankar, Uma
2018-12-11 20:38 ` [v2 08/14] drm: Enable HDR infoframe support Uma Shankar
2018-12-21 8:40 ` Sharma, Shashank
2019-01-08 6:53 ` Shankar, Uma
2018-12-11 20:38 ` [v2 09/14] drm/i915: Write HDR infoframe and send to panel Uma Shankar
2018-12-21 8:43 ` Sharma, Shashank
2019-01-08 6:55 ` Shankar, Uma
2018-12-11 20:38 ` [v2 10/14] drm/i915: [DO NOT MERGE] hack for glk board outputs Uma Shankar
2018-12-11 20:38 ` [v2 11/14] drm/i915: Add HLG EOTF Uma Shankar
2018-12-21 8:47 ` Sharma, Shashank
2019-01-08 6:56 ` Shankar, Uma
2018-12-11 20:38 ` Uma Shankar [this message]
2018-12-21 8:53 ` [v2 12/14] drm/i915: Enable infoframes on GLK+ for HDR Sharma, Shashank
2018-12-11 20:38 ` [v2 13/14] drm/i915:Enabled Modeset when HDR Infoframe changes Uma Shankar
2018-12-11 20:38 ` [v2 14/14] drivers/video: Constantify function argument for HDMI infoframe log Uma Shankar
2018-12-21 8:58 ` Sharma, Shashank
2019-01-08 7:29 ` Shankar, Uma
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