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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: [v4 11/12] drm/i915: Enable infoframes on GLK+ for HDR
Date: Tue,  8 Jan 2019 14:41:26 +0530	[thread overview]
Message-ID: <1546938687-27306-12-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1546938687-27306-1-git-send-email-uma.shankar@intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.

v2: Addressed Shashank's review comment.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  4 ++++
 drivers/gpu/drm/i915/intel_hdmi.c | 13 ++++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d9..ffeb5c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4615,6 +4615,7 @@ enum {
 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
 /* HSW and later: */
 #define   DRM_DIP_ENABLE		(1 << 28)
+#define   VIDEO_DIP_ENABLE_DRM_GLK	(1 << 28)
 #define   PSR_VSC_BIT_7_SET		(1 << 27)
 #define   VSC_SELECT_MASK		(0x3 << 25)
 #define   VSC_SELECT_SHIFT		25
@@ -8039,6 +8040,7 @@ enum {
 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
@@ -8052,6 +8054,7 @@ enum {
 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
@@ -8076,6 +8079,7 @@ enum {
 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8f2be2b..c4657f5 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -123,6 +123,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
 		return VIDEO_DIP_ENABLE_SPD_HSW;
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return VIDEO_DIP_ENABLE_VS_HSW;
+	case HDMI_INFOFRAME_TYPE_DRM:
+		return VIDEO_DIP_ENABLE_DRM_GLK;
 	default:
 		MISSING_CASE(type);
 		return 0;
@@ -146,6 +148,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
 		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+	case HDMI_INFOFRAME_TYPE_DRM:
+		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 	default:
 		MISSING_CASE(type);
 		return INVALID_MMIO_REG;
@@ -432,7 +436,8 @@ static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
 
 	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+		      VIDEO_DIP_ENABLE_DRM_GLK);
 }
 
 /*
@@ -890,7 +895,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
 
 	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+		 VIDEO_DIP_ENABLE_DRM_GLK);
 
 	if (!enable) {
 		I915_WRITE(reg, val);
@@ -909,7 +915,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
 	intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 
 	/* Set Dynamic Range and Mastering Infoframe if supported and changed */
-	if (conn_state->hdr_metadata_changed)
+	if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+		conn_state->hdr_metadata_changed)
 		intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
 }
 
-- 
1.9.1

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  parent reply	other threads:[~2019-01-08  9:11 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-08  9:11 [v4 00/12] Add HDR Metadata Parsing and handling in DRM layer Uma Shankar
2019-01-08  9:11 ` [v4 01/12] drm: Add HDR source metadata property Uma Shankar
2019-01-09  0:51   ` [Intel-gfx] " kbuild test robot
2019-01-10 11:03   ` Liviu Dudau
2019-01-08  9:11 ` [v4 02/12] drm: Parse HDR metadata info from EDID Uma Shankar
2019-01-08  9:11 ` [v4 03/12] drm: Parse Colorimetry data block " Uma Shankar
2019-01-09  2:57   ` [Intel-gfx] " kbuild test robot
2019-01-08  9:11 ` [v4 04/12] drm/i915: Attach HDR metadata property to connector Uma Shankar
2019-01-08  9:11 ` [v4 05/12] drm: Add HDR capability field to plane structure Uma Shankar
2019-01-09  5:09   ` kbuild test robot
2019-01-10 10:47   ` Liviu Dudau
2019-01-10 11:45     ` Shankar, Uma
2019-01-08  9:11 ` [v4 06/12] drm: Implement HDR output metadata set and get property handling Uma Shankar
2019-01-08  9:11 ` [v4 07/12] drm: Enable HDR infoframe support Uma Shankar
2019-01-09  2:19   ` kbuild test robot
2019-01-09  7:19   ` kbuild test robot
2019-01-08  9:11 ` [v4 08/12] drm/i915: Write HDR infoframe and send to panel Uma Shankar
2019-01-08  9:11 ` [v4 09/12] drm/i915: [DO NOT MERGE] hack for glk board outputs Uma Shankar
2019-01-08  9:11 ` [v4 10/12] drm/i915: Add HLG EOTF Uma Shankar
2019-01-08 19:45   ` Matt Roper
2019-01-09 12:08     ` Shankar, Uma
2019-01-08  9:11 ` Uma Shankar [this message]
2019-01-08  9:11 ` [v4 12/12] drm/i915:Enabled Modeset when HDR Infoframe changes Uma Shankar
2019-01-08 10:23 ` ✗ Fi.CI.CHECKPATCH: warning for Add HDR Metadata Parsing and handling in DRM layer (rev4) Patchwork
2019-01-08 10:29 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-01-08 10:41 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-08 14:08 ` ✓ Fi.CI.IGT: " Patchwork

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