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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com
Subject: [v8 3/5] drm/i915/icl: Enable ICL Pipe CSC block
Date: Mon, 11 Feb 2019 14:56:28 +0530	[thread overview]
Message-ID: <1549877190-4509-4-git-send-email-uma.shankar@intel.com> (raw)
In-Reply-To: <1549877190-4509-1-git-send-email-uma.shankar@intel.com>

Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.

ToDO: Extend the ABI to accept 32 bit coefficient values
instead of 16bit for future platforms.

v2: Addressed Maarten's review comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Addressed Matt's review comments.

v5: Addressed Ville's review comments.

v6: Separated pipe output csc programming from regular csc.

v7: Rebase

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    | 9 ++++++---
 drivers/gpu/drm/i915/intel_color.c | 5 ++++-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13a207a..4cb0013 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9885,10 +9885,13 @@ enum skl_power_gate {
 #define _PIPE_A_CSC_COEFF_BU	0x4901c
 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
 #define _PIPE_A_CSC_COEFF_BV	0x49024
+
 #define _PIPE_A_CSC_MODE	0x49028
-#define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
-#define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
-#define   CSC_MODE_YUV_TO_RGB		(1 << 0)
+#define  ICL_CSC_ENABLE			(1 << 31)
+#define  CSC_BLACK_SCREEN_OFFSET	(1 << 2)
+#define  CSC_POSITION_BEFORE_GAMMA	(1 << 1)
+#define  CSC_MODE_YUV_TO_RGB		(1 << 0)
+
 #define _PIPE_A_CSC_PREOFF_HI	0x49030
 #define _PIPE_A_CSC_PREOFF_ME	0x49034
 #define _PIPE_A_CSC_PREOFF_LO	0x49038
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0fcaae4..826f8a8 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -243,7 +243,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 
-		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+		if (INTEL_GEN(dev_priv) >= 11)
+			I915_WRITE(PIPE_CSC_MODE(pipe), ICL_CSC_ENABLE);
+		else
+			I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 	} else {
 		u32 mode = CSC_MODE_YUV_TO_RGB;
 
-- 
1.9.1

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  parent reply	other threads:[~2019-02-11  9:02 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-11  9:26 [v8 0/5] Add support for Gen 11 pipe color features Uma Shankar
2019-02-11  9:26 ` [v8 1/5] drm/i915/glk: Fix degamma lut programming Uma Shankar
2019-02-11  9:26 ` [v8 2/5] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
2019-02-11 11:20   ` Maarten Lankhorst
2019-02-11 13:01     ` Shankar, Uma
2019-02-11 13:24       ` Maarten Lankhorst
2019-02-11 13:27         ` Shankar, Uma
2019-02-11  9:26 ` Uma Shankar [this message]
2019-02-11  9:26 ` [v8 4/5] drm/i915/icl: Enable pipe output csc Uma Shankar
2019-02-11  9:26 ` [v8 5/5] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
2019-02-11 11:22   ` Maarten Lankhorst
2019-02-11 11:25 ` ✓ Fi.CI.IGT: success for Add support for Gen 11 pipe color features (rev8) Patchwork

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