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From: Abel Vesa <abel.vesa@nxp.com>
To: Rob Herring <robh@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Lucas Stach <l.stach@pengutronix.de>,
	Angus Ainslie <angus.ainslie@puri.sm>
Cc: Fabio Estevam <fabio.estevam@nxp.com>,
	Anson Huang <anson.huang@nxp.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	dl-linux-imx <linux-imx@nxp.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Abel Vesa <abel.vesa@nxp.com>
Subject: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties
Date: Fri, 15 Feb 2019 18:07:24 +0000	[thread overview]
Message-ID: <1550254032-16451-4-git-send-email-abel.vesa@nxp.com> (raw)
In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com>

Add the 0.8GHz and 1GHz opps. According to the datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf
section 3.1.3 Operating ranges.

The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
The 1GHz runs in overdrive mode with the regulator set to 1V.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 1a89062..ebdec9e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -91,6 +91,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_1: cpu@1 {
@@ -101,6 +102,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_2: cpu@2 {
@@ -111,6 +113,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_3: cpu@3 {
@@ -121,6 +124,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_L2: l2-cache0 {
@@ -666,6 +670,25 @@
 			status = "disabled";
 		};
 
+
+		a53_0_opp_table: opp-table {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-800000000 {
+				opp-hz = /bits/ 64 <800000000>;
+				opp-microvolt = <900000>;
+				clock-latency-ns = <150000>;
+			};
+
+			opp-1000000000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				opp-microvolt = <1000000>;
+				clock-latency-ns = <150000>;
+				opp-suspend;
+			};
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>,	/* GIC Dist */
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com>
To: Rob Herring <robh@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	Lucas Stach <l.stach@pengutronix.de>,
	Angus Ainslie <angus.ainslie@puri.sm>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Abel Vesa <abel.vesa@nxp.com>, Anson Huang <anson.huang@nxp.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	dl-linux-imx <linux-imx@nxp.com>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties
Date: Fri, 15 Feb 2019 18:07:24 +0000	[thread overview]
Message-ID: <1550254032-16451-4-git-send-email-abel.vesa@nxp.com> (raw)
In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com>

Add the 0.8GHz and 1GHz opps. According to the datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf
section 3.1.3 Operating ranges.

The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
The 1GHz runs in overdrive mode with the regulator set to 1V.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 1a89062..ebdec9e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -91,6 +91,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_1: cpu@1 {
@@ -101,6 +102,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_2: cpu@2 {
@@ -111,6 +113,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_3: cpu@3 {
@@ -121,6 +124,7 @@
 			clocks = <&clk IMX8MQ_CLK_ARM>;
 			enable-method = "psci";
 			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_0_opp_table>;
 		};
 
 		A53_L2: l2-cache0 {
@@ -666,6 +670,25 @@
 			status = "disabled";
 		};
 
+
+		a53_0_opp_table: opp-table {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-800000000 {
+				opp-hz = /bits/ 64 <800000000>;
+				opp-microvolt = <900000>;
+				clock-latency-ns = <150000>;
+			};
+
+			opp-1000000000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				opp-microvolt = <1000000>;
+				clock-latency-ns = <150000>;
+				opp-suspend;
+			};
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>,	/* GIC Dist */
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-02-15 18:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-15 18:07 [PATCH v2 0/3] arm: dts: imx8mq: Add cpufreq support Abel Vesa
2019-02-15 18:07 ` Abel Vesa
2019-02-15 18:07 ` Abel Vesa
2019-02-15 18:07 ` [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Abel Vesa
2019-02-15 18:07   ` Abel Vesa
2019-02-15 18:07   ` Abel Vesa
2019-02-15 18:07 ` [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Abel Vesa
2019-02-15 18:07   ` Abel Vesa
2019-02-15 18:07   ` Abel Vesa
2019-02-28 14:15   ` Shawn Guo
2019-02-28 14:15     ` Shawn Guo
2019-02-28 14:15     ` Shawn Guo
2019-02-28 14:29     ` Abel Vesa
2019-02-28 14:29       ` Abel Vesa
2019-02-28 14:29       ` Abel Vesa
2019-02-15 18:07 ` Abel Vesa [this message]
2019-02-15 18:07   ` [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Abel Vesa
2019-02-15 18:07   ` Abel Vesa
2019-02-28 14:20   ` Shawn Guo
2019-02-28 14:20     ` Shawn Guo
2019-02-28 14:20     ` Shawn Guo
2019-02-28 14:28     ` Abel Vesa
2019-02-28 14:28       ` Abel Vesa
2019-02-28 14:28       ` Abel Vesa

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