From: Andrew Murray <andrew.murray@arm.com> To: Christoffer Dall <christoffer.dall@arm.com>, Marc Zyngier <marc.zyngier@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Julien Thierry <julien.thierry@arm.com> Subject: [PATCH v3 0/6] KVM: arm/arm64: add support for chained counters Date: Mon, 18 Feb 2019 13:47:58 +0000 [thread overview] Message-ID: <1550497684-26046-1-git-send-email-andrew.murray@arm.com> (raw) ARMv8 provides support for chained PMU counters, where an event type of 0x001E is set for odd-numbered counters, the event counter will increment by one for each overflow of the preceding even-numbered counter. Let's emulate this in KVM by creating a 64 bit perf counter when a user chains two emulated counters together. Testing has been performed by hard-coding hwc->sample_period in __hw_perf_event_init (arm_pmu.c) to a small value, this results in regular overflows (for non sampling events). The following command was then used to measure chained and non-chained instruction cycles: perf stat -e armv8_pmuv3/long=1,inst_retired/u \ -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ count=10 | gzip > /dev/null The reported values were identical (and for non-chained was in the same ballpark when running on a kernel without this patchset). Debug was added to verify that the guest received overflow interrupts for the chain counter. Changes since v2: - Rebased onto v5.0-rc7 - Add check for cycle counter in correct patch - Minor style, naming and comment changes - Extract armv8pmu_evtype_is_chain from arch/arm64/kernel/perf_event.c into a common header that KVM can use Changes since v1: - Rename kvm_pmu_{enable,disable}_counter to reflect that they can operate on multiple counters at once and use these functions where possible - Fix bugs with overflow handing, kvm_pmu_get_counter_value did not take into consideration the perf counter value overflowing the low counter - Ensure PMCCFILTR_EL0 is used when operating on the cycle counter - Rename kvm_pmu_reenable_enabled_{pair, single} and similar - Always create perf event disabled to simplify logic elsewhere - Move PMCNTENSET_EL0 test to kvm_pmu_enable_counter_mask Andrew Murray (6): KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions KVM: arm/arm64: extract duplicated code to own function KVM: arm/arm64: re-create event when setting counter value KVM: arm/arm64: lazily create perf events on enable arm64: perf: extract chain helper into header KVM: arm/arm64: support chained PMU counters arch/arm64/include/asm/perf_event.h | 5 + arch/arm64/kernel/perf_event.c | 2 +- arch/arm64/kvm/sys_regs.c | 4 +- include/kvm/arm_pmu.h | 9 +- virt/kvm/arm/pmu.c | 410 ++++++++++++++++++++++++++++++------ 5 files changed, 360 insertions(+), 70 deletions(-) -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Murray <andrew.murray@arm.com> To: Christoffer Dall <christoffer.dall@arm.com>, Marc Zyngier <marc.zyngier@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Julien Thierry <julien.thierry@arm.com> Subject: [PATCH v3 0/6] KVM: arm/arm64: add support for chained counters Date: Mon, 18 Feb 2019 13:47:58 +0000 [thread overview] Message-ID: <1550497684-26046-1-git-send-email-andrew.murray@arm.com> (raw) ARMv8 provides support for chained PMU counters, where an event type of 0x001E is set for odd-numbered counters, the event counter will increment by one for each overflow of the preceding even-numbered counter. Let's emulate this in KVM by creating a 64 bit perf counter when a user chains two emulated counters together. Testing has been performed by hard-coding hwc->sample_period in __hw_perf_event_init (arm_pmu.c) to a small value, this results in regular overflows (for non sampling events). The following command was then used to measure chained and non-chained instruction cycles: perf stat -e armv8_pmuv3/long=1,inst_retired/u \ -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ count=10 | gzip > /dev/null The reported values were identical (and for non-chained was in the same ballpark when running on a kernel without this patchset). Debug was added to verify that the guest received overflow interrupts for the chain counter. Changes since v2: - Rebased onto v5.0-rc7 - Add check for cycle counter in correct patch - Minor style, naming and comment changes - Extract armv8pmu_evtype_is_chain from arch/arm64/kernel/perf_event.c into a common header that KVM can use Changes since v1: - Rename kvm_pmu_{enable,disable}_counter to reflect that they can operate on multiple counters at once and use these functions where possible - Fix bugs with overflow handing, kvm_pmu_get_counter_value did not take into consideration the perf counter value overflowing the low counter - Ensure PMCCFILTR_EL0 is used when operating on the cycle counter - Rename kvm_pmu_reenable_enabled_{pair, single} and similar - Always create perf event disabled to simplify logic elsewhere - Move PMCNTENSET_EL0 test to kvm_pmu_enable_counter_mask Andrew Murray (6): KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions KVM: arm/arm64: extract duplicated code to own function KVM: arm/arm64: re-create event when setting counter value KVM: arm/arm64: lazily create perf events on enable arm64: perf: extract chain helper into header KVM: arm/arm64: support chained PMU counters arch/arm64/include/asm/perf_event.h | 5 + arch/arm64/kernel/perf_event.c | 2 +- arch/arm64/kvm/sys_regs.c | 4 +- include/kvm/arm_pmu.h | 9 +- virt/kvm/arm/pmu.c | 410 ++++++++++++++++++++++++++++++------ 5 files changed, 360 insertions(+), 70 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2019-02-18 13:47 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-18 13:47 Andrew Murray [this message] 2019-02-18 13:47 ` [PATCH v3 0/6] KVM: arm/arm64: add support for chained counters Andrew Murray 2019-02-18 13:47 ` [PATCH v3 1/6] KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions Andrew Murray 2019-02-18 13:47 ` Andrew Murray 2019-02-18 13:48 ` [PATCH v3 2/6] KVM: arm/arm64: extract duplicated code to own function Andrew Murray 2019-02-18 13:48 ` Andrew Murray 2019-02-18 13:48 ` [PATCH v3 3/6] KVM: arm/arm64: re-create event when setting counter value Andrew Murray 2019-02-18 13:48 ` Andrew Murray 2019-02-18 13:48 ` [PATCH v3 4/6] KVM: arm/arm64: lazily create perf events on enable Andrew Murray 2019-02-18 13:48 ` Andrew Murray 2019-02-18 13:48 ` [PATCH v3 5/6] arm64: perf: extract chain helper into header Andrew Murray 2019-02-18 13:48 ` Andrew Murray 2019-02-18 13:48 ` [PATCH v3 6/6] KVM: arm/arm64: support chained PMU counters Andrew Murray 2019-02-18 13:48 ` Andrew Murray 2019-02-20 13:36 ` Marc Zyngier 2019-02-20 13:36 ` Marc Zyngier 2019-02-20 19:34 ` Andrew Murray 2019-02-20 19:34 ` Andrew Murray
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1550497684-26046-1-git-send-email-andrew.murray@arm.com \ --to=andrew.murray@arm.com \ --cc=christoffer.dall@arm.com \ --cc=julien.thierry@arm.com \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=marc.zyngier@arm.com \ --cc=suzuki.poulose@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.