From: Aisheng Dong <aisheng.dong@nxp.com> To: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Cc: Aisheng Dong <aisheng.dong@nxp.com>, Mark Rutland <mark.rutland@arm.com>, "dongas86@gmail.com" <dongas86@gmail.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, "shawnguo@kernel.org" <shawnguo@kernel.org> Subject: [PATCH 12/14] arm64: dts: imx8qm: add dma ss support Date: Thu, 21 Feb 2019 18:25:39 +0000 [thread overview] Message-ID: <1550773093-13349-13-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS while it has one more instance for each of LPUART, ADC and LPI2C. And unlike MX8QXP that flexcan clocks are shared between multiple CAN instances, MX8QM has separate flexcan clock slice. So we reuse the most part of common imx8-ss-dma.dtsi and add new things based on it. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 171 +++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 0000000..7645612 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ +&dma_subsys { + adc1_clk: clock-adc1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_ADC_1>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "adc1_clk"; + }; + + can1_clk: clock-can1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_CAN_1>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "can1_clk"; + }; + + can2_clk: clock-can2 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_CAN_2>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "can2_clk"; + }; + + uart4_clk: clock-uart4 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_UART_4>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "uart4_clk"; + }; + + uart4_lpcg: clock-controller@5a4a0000 { + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&uart4_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + }; +}; + +&adc0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&can0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_pwm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&dma_lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&dma_i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Aisheng Dong <aisheng.dong@nxp.com> To: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Cc: Aisheng Dong <aisheng.dong@nxp.com>, Mark Rutland <mark.rutland@arm.com>, "dongas86@gmail.com" <dongas86@gmail.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "catalin.marinas@arm.com" <catalin.marinas@arm.com>, "will.deacon@arm.com" <will.deacon@arm.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, "shawnguo@kernel.org" <shawnguo@kernel.org> Subject: [PATCH 12/14] arm64: dts: imx8qm: add dma ss support Date: Thu, 21 Feb 2019 18:25:39 +0000 [thread overview] Message-ID: <1550773093-13349-13-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS while it has one more instance for each of LPUART, ADC and LPI2C. And unlike MX8QXP that flexcan clocks are shared between multiple CAN instances, MX8QM has separate flexcan clock slice. So we reuse the most part of common imx8-ss-dma.dtsi and add new things based on it. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 171 +++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 0000000..7645612 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ +&dma_subsys { + adc1_clk: clock-adc1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_ADC_1>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "adc1_clk"; + }; + + can1_clk: clock-can1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_CAN_1>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "can1_clk"; + }; + + can2_clk: clock-can2 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_CAN_2>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "can2_clk"; + }; + + uart4_clk: clock-uart4 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = <IMX_SC_R_UART_4>; + clk-type = <IMX_SC_PM_CLK_PER>; + clock-output-names = "uart4_clk"; + }; + + uart4_lpcg: clock-controller@5a4a0000 { + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&uart4_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + }; +}; + +&adc0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&can0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_pwm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&dma_lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&dma_i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-21 18:25 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-21 18:24 [PATCH 00/14] arm64: dts: imx8: architecture improvement and adding imx8qm support Aisheng Dong 2019-02-21 18:24 ` [PATCH 01/14] arm64: dts: imx8qxp: orginize dts in subsystems Aisheng Dong 2019-02-21 18:24 ` Aisheng Dong 2019-04-02 4:16 ` Shawn Guo 2019-04-02 4:16 ` Shawn Guo 2019-04-02 14:38 ` Aisheng Dong 2019-04-02 14:38 ` Aisheng Dong 2019-02-21 18:24 ` [PATCH 02/14] arm64: dts: imx8: add lsio scu clocks Aisheng Dong 2019-02-21 18:24 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 03/14] arm64: dts: imx8: add conn " Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 04/14] arm64: dts: imx8: add adma " Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 05/14] arm64: dts: imx8: add lsio lpcg clocks Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 06/14] arm64: dts: imx8: add conn " Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 07/14] arm64: dts: imx8: add adma " Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 08/14] arm64: dts: imx8: switch to new clock binding Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 09/14] arm64: dts: imx8qm: add lsio ss support Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 10/14] arm64: dts: imx8qm: add conn " Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 11/14] arm64: dts: imx8: split adma ss into dma and audio ss Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong [this message] 2019-02-21 18:25 ` [PATCH 12/14] arm64: dts: imx8qm: add dma ss support Aisheng Dong 2019-02-21 18:25 ` [PATCH 13/14] arm64: dts: imx: add imx8qm common dts file Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-02-21 18:25 ` [PATCH 14/14] arm64: dts: imx: add imx8qm mek support Aisheng Dong 2019-02-21 18:25 ` Aisheng Dong 2019-03-26 13:16 ` [PATCH 00/14] arm64: dts: imx8: architecture improvement and adding imx8qm support Aisheng Dong 2019-04-02 4:28 ` Shawn Guo 2019-04-02 14:42 ` Aisheng Dong
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