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From: biju.das@bp.renesas.com (Biju Das)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core
Date: Fri, 22 Mar 2019 09:19:22 +0000	[thread overview]
Message-ID: <1553246370-60751-2-git-send-email-biju.das@bp.renesas.com> (raw)
In-Reply-To: <1553246370-60751-1-git-send-email-biju.das@bp.renesas.com>

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 9b55a05ebfbe41bfb4c2aa98a81a46f2031e599f)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 872efa7..5bea23e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -48,7 +48,6 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* 1 core only at this point */
 		a53_0: cpu at 0 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0>;
@@ -58,6 +57,15 @@
 			enable-method = "psci";
 		};
 
+		a53_1: cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <1>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+		};
+
 		L2_CA53: cache-controller-0 {
 			compatible = "cache";
 			power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
@@ -82,8 +90,9 @@
 
 	pmu_a53 {
 		compatible = "arm,cortex-a53-pmu";
-		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&a53_0>;
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>, <&a53_1>;
 	};
 
 	psci {
@@ -423,7 +432,7 @@
 			      <0x0 0xf1040000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x20000>;
 			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&cpg CPG_MOD 408>;
 			clock-names = "clk";
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@@ -438,10 +447,10 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	/* External USB clocks - can be overridden by the board */
-- 
2.7.4

  reply	other threads:[~2019-03-22  9:19 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-22  9:19 [cip-dev] [PATCH 0/9] Add SMP/INTC-EX/PFC/GPIO support Biju Das
2019-03-22  9:19 ` Biju Das [this message]
2019-04-10 23:14   ` [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core nobuhiro1.iwamatsu at toshiba.co.jp
2019-04-11  6:54     ` Biju Das
2019-04-11  6:59       ` Biju Das
2019-04-11  9:34       ` Nobuhiro Iwamatsu
2019-03-22  9:19 ` [cip-dev] [PATCH 2/9] pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotive Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 3/9] pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and function Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 4/9] arm64: dts: renesas: r8a774c0: Add INTC-EX device node Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 5/9] arm64: dts: renesas: r8a774c0: Add PFC support Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 6/9] dt-bindings: gpio: rcar: Add r8a774a1 (RZ/G2M) support Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 7/9] dt-bindings: gpio: rcar: Add r8a774c0 (RZ/G2E) support Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 8/9] arm64: dts: renesas: r8a774c0: Add GPIO device nodes Biju Das
2019-03-22  9:19 ` [cip-dev] [PATCH 9/9] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2 Biju Das

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