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From: Wu Hao <hao.wu@intel.com>
To: atull@kernel.org, mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: linux-api@vger.kernel.org, Wu Hao <hao.wu@intel.com>,
	Xu Yilun <yilun.xu@intel.com>
Subject: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth
Date: Mon, 25 Mar 2019 11:07:29 +0800	[thread overview]
Message-ID: <1553483264-5379-3-git-send-email-hao.wu@intel.com> (raw)
In-Reply-To: <1553483264-5379-1-git-send-email-hao.wu@intel.com>

Current driver checks if input bitstream file size is aligned or
not per PR data width (default 32bits). It requires one additional
step for end user when they generate the bitstream file, padding
extra zeros to bitstream file to align its size per PR data width,
but they don't have to as hardware will drop extra padding bytes
automatically.

In order to simplify the user steps, this patch aligns PR buffer
size per PR data width in driver, to allow user to pass unaligned
size bitstream files to driver.

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
---
 drivers/fpga/dfl-fme-pr.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index d9ca955..c1fb1fe 100644
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -74,6 +74,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	struct dfl_fme *fme;
 	unsigned long minsz;
 	void *buf = NULL;
+	size_t length;
 	int ret = 0;
 	u64 v;
 
@@ -85,9 +86,6 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	if (port_pr.argsz < minsz || port_pr.flags)
 		return -EINVAL;
 
-	if (!IS_ALIGNED(port_pr.buffer_size, 4))
-		return -EINVAL;
-
 	/* get fme header region */
 	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
 					       FME_FEATURE_ID_HEADER);
@@ -103,7 +101,13 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 		       port_pr.buffer_size))
 		return -EFAULT;
 
-	buf = vmalloc(port_pr.buffer_size);
+	/*
+	 * align PR buffer per PR bandwidth, as HW ignores the extra padding
+	 * data automatically.
+	 */
+	length = ALIGN(port_pr.buffer_size, 4);
+
+	buf = vmalloc(length);
 	if (!buf)
 		return -ENOMEM;
 
@@ -140,7 +144,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 	fpga_image_info_free(region->info);
 
 	info->buf = buf;
-	info->count = port_pr.buffer_size;
+	info->count = length;
 	info->region_id = port_pr.port_id;
 	region->info = info;
 
-- 
2.7.4


  parent reply	other threads:[~2019-03-25  3:23 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25  3:07 [PATCH 00/17] add new features for FPGA DFL drivers Wu Hao
2019-03-25  3:07 ` [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-03-25 17:28   ` Alan Tull
2019-04-01 19:54   ` Moritz Fischer
2019-04-02  4:38     ` Wu Hao
2019-04-02 13:33       ` Moritz Fischer
2019-03-25  3:07 ` Wu Hao [this message]
2019-03-25 17:50   ` [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth Alan Tull
2019-03-26  0:28     ` Wu Hao
2019-03-28 18:50       ` Alan Tull
2019-03-25  3:07 ` [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-03-25 18:48   ` Alan Tull
2019-03-25 22:53   ` Scott Wood
2019-03-25 22:58     ` Scott Wood
2019-03-26 19:33       ` Alan Tull
2019-03-26 21:22         ` Scott Wood
2019-03-27  4:37           ` Wu Hao
2019-03-27  6:10             ` Scott Wood
2019-03-27  6:10               ` Scott Wood
2019-03-27  6:03               ` Wu Hao
2019-03-27  5:10       ` Wu Hao
2019-03-27  6:19         ` Scott Wood
2019-03-27  7:10           ` Wu Hao
2019-03-27  5:46     ` Wu Hao
2019-03-25  3:07 ` [PATCH 04/17] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-03-25  3:07 ` [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-03-28 22:03   ` Alan Tull
2019-03-25  3:07 ` [PATCH 06/17] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-03-28 22:03   ` Alan Tull
2019-03-25  3:07 ` [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-03-28 17:13   ` Alan Tull
2019-03-25  3:07 ` [PATCH 08/17] fpga: dfl: afu: add userclock " Wu Hao
2019-04-01 21:41   ` Alan Tull
2019-03-25  3:07 ` [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-04-02 15:09   ` Moritz Fischer
2019-04-11 20:55     ` Alan Tull
2019-03-25  3:07 ` [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-04-02 15:42   ` Moritz Fischer
2019-04-02 15:50   ` Moritz Fischer
2019-04-11 20:45     ` Alan Tull
2019-03-25  3:07 ` [PATCH 11/17] fpga: dfl: afu: add error reporting support Wu Hao
2019-04-09 20:57   ` Alan Tull
2019-04-10  1:43     ` Wu Hao
2019-03-25  3:07 ` [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-04-02 15:07   ` Moritz Fischer
2019-04-11 20:41     ` Alan Tull
2019-03-25  3:07 ` [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-04-09 21:05   ` Alan Tull
2019-03-25  3:07 ` [PATCH 14/17] fpga: dfl: fme: add thermal management support Wu Hao
2019-04-02 14:59   ` Moritz Fischer
2019-04-03 16:31     ` Wu Hao
2019-04-03 18:09       ` Moritz Fischer
2019-04-03 23:43         ` Wu Hao
2019-03-25  3:07 ` [PATCH 15/17] fpga: dfl: fme: add power " Wu Hao
2019-04-11 20:07   ` Alan Tull
2019-04-12  2:50     ` Wu Hao
2019-04-15 21:17       ` Alan Tull
2019-04-17  7:36         ` Wu Hao
2019-04-12 21:05     ` Moritz Fischer
2019-04-17  7:31       ` Wu Hao
2019-03-25  3:07 ` [PATCH 16/17] fpga: dfl: fme: add global error reporting support Wu Hao
2019-04-09 21:35   ` Alan Tull
2019-04-10  1:34     ` Wu Hao
2019-03-25  3:07 ` [PATCH 17/17] fpga: dfl: fme: add performance " Wu Hao

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