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From: fabrizio.castro@bp.renesas.com (Fabrizio Castro)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH 4.19y 03/10] pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3
Date: Mon,  1 Apr 2019 14:55:40 +0100	[thread overview]
Message-ID: <1554126947-32747-4-git-send-email-fabrizio.castro@bp.renesas.com> (raw)
In-Reply-To: <1554126947-32747-1-git-send-email-fabrizio.castro@bp.renesas.com>

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit 117774fbe6beae3fd4f1fed5b7f596acdd90a2ed upstream.

Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc:
r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control
Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3.
Hence on R-Car E3, SDHI voltage state is lost after system resume.

Fix this by registering the I/O Control Registers on R-Car E3, too.

Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 8c06d72..9ebc7bc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -5004,6 +5004,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
 
 	.cfg_regs = pinmux_config_regs,
 	.bias_regs = pinmux_bias_regs,
+	.ioctrl_regs = pinmux_ioctrl_regs,
 
 	.pinmux_data = pinmux_data,
 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
-- 
2.7.4

  parent reply	other threads:[~2019-04-01 13:55 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-01 13:55 [cip-dev] [PATCH 4.19y 00/10] Pinctrl driver updates for RZ/G2E Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 01/10] pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functions Fabrizio Castro
2019-04-09 21:03   ` Pavel Machek
2019-04-10  9:16     ` Fabrizio Castro
2019-04-10  9:28       ` Fabrizio Castro
2019-04-12 20:28         ` [cip-dev] Renesas patches was " Pavel Machek
2019-04-15  8:10           ` Fabrizio Castro
2019-04-10 23:31       ` [cip-dev] " nobuhiro1.iwamatsu at toshiba.co.jp
2019-04-12  8:04   ` Pavel Machek
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 02/10] pinctrl: sh-pfc: r8a77990: Add CAN FD " Fabrizio Castro
2019-04-01 13:55 ` Fabrizio Castro [this message]
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 04/10] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 SEL_I2C1 field width Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 05/10] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0 Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 06/10] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2 Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 07/10] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 08/10] pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 09/10] pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions Fabrizio Castro
2019-04-01 13:55 ` [cip-dev] [PATCH 4.19y 10/10] pinctrl: sh-pfc: r8a77990: Add DRIF " Fabrizio Castro

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