All of lore.kernel.org
 help / color / mirror / Atom feed
From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: mturquette@baylibre.com, sboyd@kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com,
	Elaine Zhang <zhangqing@rock-chips.com>
Subject: [PATCH v1 2/6] clk: rockchip: fix up the frac clk get rate error
Date: Wed,  3 Apr 2019 17:42:25 +0800	[thread overview]
Message-ID: <1554284549-24916-3-git-send-email-zhangqing@rock-chips.com> (raw)
In-Reply-To: <1554284549-24916-1-git-send-email-zhangqing@rock-chips.com>

support fractional divider with only one level parent clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index e04bf300ea0a..0256a99f06f3 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -195,16 +195,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
 	if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
 	    (fd->max_prate && fd->max_prate < p_rate)) {
 		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
-		p_parent_rate = clk_hw_get_rate(p_parent);
-		*parent_rate = p_parent_rate;
-		if (fd->max_prate && p_parent_rate > fd->max_prate) {
-			div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
-			*parent_rate = p_parent_rate / div;
+		if (!p_parent) {
+			*parent_rate = p_rate;
+		} else {
+			p_parent_rate = clk_hw_get_rate(p_parent);
+			*parent_rate = p_parent_rate;
+			if (fd->max_prate && p_parent_rate > fd->max_prate) {
+				div = DIV_ROUND_UP(p_parent_rate,
+						   fd->max_prate);
+				*parent_rate = p_parent_rate / div;
+			}
 		}
 
 		if (*parent_rate < rate * 20) {
-			pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
-			       clk_hw_get_name(hw), *parent_rate, rate);
+			pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+				clk_hw_get_name(hw), *parent_rate, rate);
 			*m = 0;
 			*n = 1;
 			return;
-- 
1.9.1




WARNING: multiple messages have this Message-ID (diff)
From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com,
	sboyd@kernel.org, mturquette@baylibre.com,
	Elaine Zhang <zhangqing@rock-chips.com>,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 2/6] clk: rockchip: fix up the frac clk get rate error
Date: Wed,  3 Apr 2019 17:42:25 +0800	[thread overview]
Message-ID: <1554284549-24916-3-git-send-email-zhangqing@rock-chips.com> (raw)
In-Reply-To: <1554284549-24916-1-git-send-email-zhangqing@rock-chips.com>

support fractional divider with only one level parent clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index e04bf300ea0a..0256a99f06f3 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -195,16 +195,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
 	if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
 	    (fd->max_prate && fd->max_prate < p_rate)) {
 		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
-		p_parent_rate = clk_hw_get_rate(p_parent);
-		*parent_rate = p_parent_rate;
-		if (fd->max_prate && p_parent_rate > fd->max_prate) {
-			div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
-			*parent_rate = p_parent_rate / div;
+		if (!p_parent) {
+			*parent_rate = p_rate;
+		} else {
+			p_parent_rate = clk_hw_get_rate(p_parent);
+			*parent_rate = p_parent_rate;
+			if (fd->max_prate && p_parent_rate > fd->max_prate) {
+				div = DIV_ROUND_UP(p_parent_rate,
+						   fd->max_prate);
+				*parent_rate = p_parent_rate / div;
+			}
 		}
 
 		if (*parent_rate < rate * 20) {
-			pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
-			       clk_hw_get_name(hw), *parent_rate, rate);
+			pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+				clk_hw_get_name(hw), *parent_rate, rate);
 			*m = 0;
 			*n = 1;
 			return;
-- 
1.9.1




_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-04-03  9:42 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03  9:42 [PATCH v1 0/6] clk: rockchip: Support for some new features Elaine Zhang
2019-04-03  9:42 ` [PATCH v1 1/6] clk: rockchip: Add supprot to limit input rate for fractional divider Elaine Zhang
2019-04-12 11:52   ` Heiko Stübner
2019-04-12 11:52     ` Heiko Stübner
2019-04-12 12:12     ` Christoph Müllner
2019-04-12 12:12       ` Christoph Müllner
2019-04-12 12:21       ` Heiko Stübner
2019-04-12 12:21         ` Heiko Stübner
2019-04-12 12:32         ` Christoph Müllner
2019-04-12 12:32           ` Christoph Müllner
2019-04-12 12:39           ` Heiko Stübner
2019-04-12 12:39             ` Heiko Stübner
2019-04-12 12:39             ` Heiko Stübner
2019-04-03  9:42 ` Elaine Zhang [this message]
2019-04-03  9:42   ` [PATCH v1 2/6] clk: rockchip: fix up the frac clk get rate error Elaine Zhang
2019-04-03  9:42 ` [PATCH v1 3/6] clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type Elaine Zhang
2019-04-03  9:42   ` Elaine Zhang
2019-04-12 11:35   ` Heiko Stübner
2019-04-12 11:35     ` Heiko Stübner
2019-04-03  9:42 ` [PATCH v1 4/6] clk: rockchip: add a clock-type for muxes based in the pmugrf Elaine Zhang
2019-04-12 11:45   ` Heiko Stübner
2019-04-12 11:45     ` Heiko Stübner
2019-04-03  9:44 ` [PATCH v1 5/6] clk: rockchip: add pll up and down when change pll freq Elaine Zhang
2019-04-03  9:44   ` Elaine Zhang
2019-04-12 12:15   ` Heiko Stübner
2019-04-12 12:15     ` Heiko Stübner
2019-04-12 17:28     ` Doug Anderson
2019-04-12 17:28       ` Doug Anderson
2019-04-03  9:44 ` [PATCH v1 6/6] clk: rockchip: support pll setting by auto Elaine Zhang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1554284549-24916-3-git-send-email-zhangqing@rock-chips.com \
    --to=zhangqing@rock-chips.com \
    --cc=heiko@sntech.de \
    --cc=huangtao@rock-chips.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=mturquette@baylibre.com \
    --cc=sboyd@kernel.org \
    --cc=xf@rock-chips.com \
    --cc=xxx@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.