From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 0/3] Fix mipi dsi pipe_config mismatch for icl
Date: Thu, 4 Apr 2019 13:36:24 +0530 [thread overview]
Message-ID: <1554365187-30575-1-git-send-email-vandita.kulkarni@intel.com> (raw)
This is series fixes the WARN_ON that we see due to
pipe_config mismatch on mipi dsi for icl.
Only DSI0 trancoder regs are read even in case of dual link mode
as the values programmed for DSI0 and DSI1 transcoder registers
are same.
Vandita Kulkarni (3):
drm/i915: Fix pipe config timing mismatch warnings
drm/i915: Fix pipe config mismatch for bpp, output format
drm/i915: Fix pixel clock and crtc clock config mismatch
drivers/gpu/drm/i915/icl_dsi.c | 88 +++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 3 +-
2 files changed, 89 insertions(+), 2 deletions(-)
--
1.9.1
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next reply other threads:[~2019-04-04 8:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 8:06 Vandita Kulkarni [this message]
2019-04-04 8:06 ` [PATCH 1/3] drm/i915: Fix pipe config timing mismatch warnings Vandita Kulkarni
2019-04-04 20:29 ` Ville Syrjälä
2019-04-05 8:25 ` Kulkarni, Vandita
2019-04-17 11:16 ` Jani Nikula
2019-04-04 8:06 ` [PATCH 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni
2019-04-04 14:06 ` kbuild test robot
2019-04-04 14:06 ` [RFC PATCH] drm/i915: gen11_dsi_get_pixel_fmt can be static kbuild test robot
2019-04-17 11:23 ` [PATCH 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Jani Nikula
2019-04-04 8:06 ` [PATCH 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni
2019-04-17 13:42 ` Jani Nikula
2019-04-04 18:13 ` ✗ Fi.CI.BAT: failure for Fix mipi dsi pipe_config mismatch for icl (rev2) Patchwork
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