From: Shaokun Zhang <zhangshaokun@hisilicon.com> To: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Cc: <qiuzhenfa@hisilicon.com>, <john.garry@huawei.com>, <guohanjun@huawei.com>, Shaokun Zhang <zhangshaokun@hisilicon.com>, "Catalin Marinas" <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, "Sudeep Holla" <sudeep.holla@arm.com>, Jeremy Linton <jeremy.linton@arm.com> Subject: [PATCH v2 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Date: Mon, 6 May 2019 14:53:57 +0800 [thread overview] Message-ID: <1557125637-9558-2-git-send-email-zhangshaokun@hisilicon.com> (raw) In-Reply-To: <1557125637-9558-1-git-send-email-zhangshaokun@hisilicon.com> cache_line_size is derived from CTR_EL0.CWG field and is called mostly for I/O device drivers. For HiSilicon certain plantform, like the Kunpeng920 server SoC, cache line sizes are different between L1/2 cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, but CTR_EL0.CWG is misreporting using L1 cache line size. We shall correct the right value which is important for I/O performance. Let's update the cache line size if it is detected from DT or PPTT information. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Jeremy Linton <jeremy.linton@arm.com> Reported-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> --- arch/arm64/include/asm/cache.h | 6 +----- arch/arm64/kernel/cacheinfo.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 926434f413fa..758af6340314 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) #define __read_mostly __attribute__((__section__(".data..read_mostly"))) -static inline int cache_line_size(void) -{ - u32 cwg = cache_type_cwg(); - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; -} +int cache_line_size(void); /* * Read the effective value of CTR_EL0. diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 0bf0a835122f..6ffe908d476c 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -28,6 +28,16 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) +int cache_line_size(void) +{ + u32 cwg = cache_type_cwg(); + + if (coherency_max_size != 0) + return coherency_max_size; + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; +} + static inline enum cache_type get_cache_type(int level) { u64 clidr; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Shaokun Zhang <zhangshaokun@hisilicon.com> To: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org> Cc: Sudeep Holla <sudeep.holla@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, john.garry@huawei.com, Will Deacon <will.deacon@arm.com>, Jeremy Linton <jeremy.linton@arm.com>, Shaokun Zhang <zhangshaokun@hisilicon.com>, qiuzhenfa@hisilicon.com, guohanjun@huawei.com Subject: [PATCH v2 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Date: Mon, 6 May 2019 14:53:57 +0800 [thread overview] Message-ID: <1557125637-9558-2-git-send-email-zhangshaokun@hisilicon.com> (raw) In-Reply-To: <1557125637-9558-1-git-send-email-zhangshaokun@hisilicon.com> cache_line_size is derived from CTR_EL0.CWG field and is called mostly for I/O device drivers. For HiSilicon certain plantform, like the Kunpeng920 server SoC, cache line sizes are different between L1/2 cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, but CTR_EL0.CWG is misreporting using L1 cache line size. We shall correct the right value which is important for I/O performance. Let's update the cache line size if it is detected from DT or PPTT information. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Jeremy Linton <jeremy.linton@arm.com> Reported-by: Zhenfa Qiu <qiuzhenfa@hisilicon.com> Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> --- arch/arm64/include/asm/cache.h | 6 +----- arch/arm64/kernel/cacheinfo.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 926434f413fa..758af6340314 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) #define __read_mostly __attribute__((__section__(".data..read_mostly"))) -static inline int cache_line_size(void) -{ - u32 cwg = cache_type_cwg(); - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; -} +int cache_line_size(void); /* * Read the effective value of CTR_EL0. diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 0bf0a835122f..6ffe908d476c 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -28,6 +28,16 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) +int cache_line_size(void) +{ + u32 cwg = cache_type_cwg(); + + if (coherency_max_size != 0) + return coherency_max_size; + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; +} + static inline enum cache_type get_cache_type(int level) { u64 clidr; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-05-06 6:55 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-06 6:53 [PATCH v2 1/2] drivers: base: cacheinfo: Add variable to record max cache line size Shaokun Zhang 2019-05-06 6:53 ` Shaokun Zhang 2019-05-06 6:53 ` Shaokun Zhang [this message] 2019-05-06 6:53 ` [PATCH v2 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Shaokun Zhang
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