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From: John Garry <john.garry@huawei.com>
To: <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>,
	<alexander.shishkin@linux.intel.com>, <jolsa@redhat.com>,
	<namhyung@kernel.org>, <tmricht@linux.ibm.com>,
	<brueckner@linux.ibm.com>, <kan.liang@linux.intel.com>,
	<ben@decadent.org.uk>, <mathieu.poirier@linaro.org>,
	<mark.rutland@arm.com>, <will.deacon@arm.com>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<zhangshaokun@hisilicon.com>, <ak@linux.intel.com>,
	John Garry <john.garry@huawei.com>
Subject: [PATCH 5/5] perf jevents: Add support for Hisi hip08 L3C PMU aliasing
Date: Mon, 10 Jun 2019 17:59:32 +0800	[thread overview]
Message-ID: <1560160772-210844-6-git-send-email-john.garry@huawei.com> (raw)
In-Reply-To: <1560160772-210844-1-git-send-email-john.garry@huawei.com>

Add support for Hisi hip08 L3C PMU event aliasing.

The kernel driver is in drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arm64/hisilicon/hip08/uncore-l3c.json     | 37 +++++++++++++++++++
 tools/perf/pmu-events/jevents.c               |  1 +
 2 files changed, 38 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
new file mode 100644
index 000000000000..5bdc1a533d5e
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -0,0 +1,37 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_sccl_l3c.rd_cpipe",
+	    "BriefDescription": "Total read accesses",
+	    "PublicDescription": "Total read accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_sccl_l3c.wr_cpipe",
+	    "BriefDescription": "Total write accesses",
+	    "PublicDescription": "Total write accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x02",
+	    "EventName": "uncore_hisi_sccl_l3c.rd_hit_cpipe",
+	    "BriefDescription": "Total read hits",
+	    "PublicDescription": "Total read hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_sccl_l3c.wr_hit_cpipe",
+	    "BriefDescription": "Total write hits",
+	    "PublicDescription": "Total write hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x04",
+	    "EventName": "uncore_hisi_sccl_l3c.victim_num",
+	    "BriefDescription": "l3c precharge commands",
+	    "PublicDescription": "l3c precharge commands",
+	    "Unit": "hisi_sccl,l3c",
+   },
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 909e53e3b5bd..7d241efd03de 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -238,6 +238,7 @@ static struct map {
 	{ "UPI LL", "uncore_upi" },
 	{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
 	{ "hisi_sccl,hha", "hisi_sccl,hha" },
+	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
 	{}
 };
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry@huawei.com>
To: <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>,
	<alexander.shishkin@linux.intel.com>, <jolsa@redhat.com>,
	<namhyung@kernel.org>, <tmricht@linux.ibm.com>,
	<brueckner@linux.ibm.com>, <kan.liang@linux.intel.com>,
	<ben@decadent.org.uk>, <mathieu.poirier@linaro.org>,
	<mark.rutland@arm.com>, <will.deacon@arm.com>
Cc: ak@linux.intel.com, John Garry <john.garry@huawei.com>,
	linux-kernel@vger.kernel.org, linuxarm@huawei.com,
	zhangshaokun@hisilicon.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/5] perf jevents: Add support for Hisi hip08 L3C PMU aliasing
Date: Mon, 10 Jun 2019 17:59:32 +0800	[thread overview]
Message-ID: <1560160772-210844-6-git-send-email-john.garry@huawei.com> (raw)
In-Reply-To: <1560160772-210844-1-git-send-email-john.garry@huawei.com>

Add support for Hisi hip08 L3C PMU event aliasing.

The kernel driver is in drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../arm64/hisilicon/hip08/uncore-l3c.json     | 37 +++++++++++++++++++
 tools/perf/pmu-events/jevents.c               |  1 +
 2 files changed, 38 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
new file mode 100644
index 000000000000..5bdc1a533d5e
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json
@@ -0,0 +1,37 @@
+[
+   {
+	    "EventCode": "0x00",
+	    "EventName": "uncore_hisi_sccl_l3c.rd_cpipe",
+	    "BriefDescription": "Total read accesses",
+	    "PublicDescription": "Total read accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x01",
+	    "EventName": "uncore_hisi_sccl_l3c.wr_cpipe",
+	    "BriefDescription": "Total write accesses",
+	    "PublicDescription": "Total write accesses",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x02",
+	    "EventName": "uncore_hisi_sccl_l3c.rd_hit_cpipe",
+	    "BriefDescription": "Total read hits",
+	    "PublicDescription": "Total read hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x03",
+	    "EventName": "uncore_hisi_sccl_l3c.wr_hit_cpipe",
+	    "BriefDescription": "Total write hits",
+	    "PublicDescription": "Total write hits",
+	    "Unit": "hisi_sccl,l3c",
+   },
+   {
+	    "EventCode": "0x04",
+	    "EventName": "uncore_hisi_sccl_l3c.victim_num",
+	    "BriefDescription": "l3c precharge commands",
+	    "PublicDescription": "l3c precharge commands",
+	    "Unit": "hisi_sccl,l3c",
+   },
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 909e53e3b5bd..7d241efd03de 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -238,6 +238,7 @@ static struct map {
 	{ "UPI LL", "uncore_upi" },
 	{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
 	{ "hisi_sccl,hha", "hisi_sccl,hha" },
+	{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
 	{}
 };
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-06-10 10:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-10  9:59 [PATCH 0/5] Perf uncore PMU event alias support for Hisi hip08 ARM64 platform John Garry
2019-06-10  9:59 ` John Garry
2019-06-10  9:59 ` [PATCH 1/5] perf pmu: Fix uncore PMU alias list for ARM64 John Garry
2019-06-10  9:59   ` John Garry
2019-06-10  9:59 ` [PATCH 2/5] perf pmu: Support more complex PMU event aliasing John Garry
2019-06-10  9:59   ` John Garry
2019-06-11 16:10   ` Jiri Olsa
2019-06-11 16:10     ` Jiri Olsa
2019-06-11 16:22     ` John Garry
2019-06-11 16:22       ` John Garry
2019-06-10  9:59 ` [PATCH 3/5] perf jevents: Add support for Hisi hip08 DDRC PMU aliasing John Garry
2019-06-10  9:59   ` John Garry
2019-06-10  9:59 ` [PATCH 4/5] perf jevents: Add support for Hisi hip08 HHA " John Garry
2019-06-10  9:59   ` John Garry
2019-06-10  9:59 ` John Garry [this message]
2019-06-10  9:59   ` [PATCH 5/5] perf jevents: Add support for Hisi hip08 L3C " John Garry

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