From: biju.das@bp.renesas.com (Biju Das)
To: cip-dev@lists.cip-project.org
Subject: [cip-dev] [PATCH 4.19.y-cip 23/23] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
Date: Mon, 15 Jul 2019 14:30:08 +0100 [thread overview]
Message-ID: <1563197408-59548-24-git-send-email-biju.das@bp.renesas.com> (raw)
In-Reply-To: <1563197408-59548-1-git-send-email-biju.das@bp.renesas.com>
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
commit 231d8908a66fa98f09553d31ad8cd5f382b29959 upstream.
This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index c47ca0b..8a2e4d8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -44,6 +44,27 @@
clock-frequency = <0>;
};
+ cluster1_opp: opp_table10 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -55,6 +76,8 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu at 1 {
@@ -64,6 +87,8 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA53: cache-controller-0 {
--
2.7.4
next prev parent reply other threads:[~2019-07-15 13:30 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-15 13:29 [cip-dev] [PATCH 4.19.y-cip 00/23] Clock enhancements Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 01/23] clk: renesas: r8a774a1: Add CPEX clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 02/23] clk: renesas: rcar-gen3: Set state when registering SD clocks Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 03/23] clk: renesas: rcar-gen3: Add documentation for " Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 04/23] clk: renesas: rcar-gen3: Add HS400 quirk for SD clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 05/23] clk: renesas: Remove usage of CLK_IS_BASIC Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 06/23] clk: renesas: r8a774a1: Add missing CANFD clock Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 07/23] clk: renesas: rcar-gen3: Factor out cpg_reg_modify() Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 08/23] clk: renesas: rcar-gen3: Add spinlock Biju Das
2019-07-16 11:17 ` Pavel Machek
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 09/23] clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 10/23] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 11/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 12/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 13/23] clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 Biju Das
2019-07-15 13:29 ` [cip-dev] [PATCH 4.19.y-cip 14/23] math64: New DIV64_U64_ROUND_CLOSEST helper Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 15/23] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Biju Das
2019-07-16 11:22 ` Pavel Machek
2019-07-16 12:01 ` Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 16/23] clk: renesas: r8a774c0: Add Z2 clock Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 17/23] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 18/23] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 19/23] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 20/23] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 21/23] clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value Biju Das
2019-07-16 11:24 ` Pavel Machek
2019-07-16 11:56 ` Biju Das
2019-07-15 13:30 ` [cip-dev] [PATCH 4.19.y-cip 22/23] clk: renesas: rcar-gen3: Remove unused variable Biju Das
2019-07-15 13:30 ` Biju Das [this message]
2019-07-15 19:50 ` [cip-dev] [PATCH 4.19.y-cip 00/23] Clock enhancements Pavel Machek
2019-07-15 21:57 ` Pavel Machek
2019-07-16 6:45 ` Biju Das
2019-07-16 11:28 ` Pavel Machek
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