From: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> To: MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Matthias Brugger <matthias.bgg@gmail.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, Viresh Kumar <viresh.kumar@linaro.org>, Nishanth Menon <nm@ti.com>, Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>, srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [v4, 2/8] cpufreq: mediatek: add clock enable for intermediate clock Date: Tue, 13 Aug 2019 21:31:47 +0800 [thread overview] Message-ID: <1565703113-31479-3-git-send-email-andrew-sh.cheng@mediatek.com> (raw) In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com> Intermediate clock is not always enabled by ccf in different projects, so cpufreq should always enable it by itself. Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> --- drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index a370577ffc73..acd9539e95de 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_free_opp_table; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_clock: + clk_disable_unprepare(inter_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -419,6 +426,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) clk_put(info->cpu_clk); if (!IS_ERR(info->inter_clk)) clk_put(info->inter_clk); + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); + clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } -- 2.12.5
WARNING: multiple messages have this Message-ID (diff)
From: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> To: MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, "Rob Herring" <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, "Matthias Brugger" <matthias.bgg@gmail.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, Viresh Kumar <viresh.kumar@linaro.org>, Nishanth Menon <nm@ti.com>, "Stephen Boyd" <sboyd@kernel.org> Cc: devicetree@vger.kernel.org, "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>, srv_heupstream@mediatek.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, fan.chen@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [v4, 2/8] cpufreq: mediatek: add clock enable for intermediate clock Date: Tue, 13 Aug 2019 21:31:47 +0800 [thread overview] Message-ID: <1565703113-31479-3-git-send-email-andrew-sh.cheng@mediatek.com> (raw) In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com> Intermediate clock is not always enabled by ccf in different projects, so cpufreq should always enable it by itself. Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> --- drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index a370577ffc73..acd9539e95de 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_free_opp_table; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_clock: + clk_disable_unprepare(inter_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -419,6 +426,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) clk_put(info->cpu_clk); if (!IS_ERR(info->inter_clk)) clk_put(info->inter_clk); + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); + clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } -- 2.12.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-08-13 13:31 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-13 13:31 [v4, 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng [not found] ` <1565703113-31479-1-git-send-email-andrew-sh.cheng-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 2019-08-13 13:31 ` [v4, 1/8] cpufreq: mediatek: change to regulator_get_optional Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-19 9:51 ` Viresh Kumar 2019-08-19 9:51 ` Viresh Kumar 2019-08-13 13:31 ` [v4, 3/8] cpufreq: mediatek: Add support for mt8183 Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-19 9:59 ` Viresh Kumar 2019-08-19 9:59 ` Viresh Kumar 2019-08-13 13:31 ` [v4, 7/8] cpufreq: mediatek: add opp notification for SVS support Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-20 3:39 ` Viresh Kumar 2019-08-20 3:39 ` Viresh Kumar 2019-10-16 2:43 ` andrew-sh.cheng 2019-10-16 2:43 ` andrew-sh.cheng 2019-10-17 6:31 ` Viresh Kumar 2019-10-17 6:31 ` Viresh Kumar 2019-10-18 9:03 ` andrew-sh.cheng 2019-10-18 9:03 ` andrew-sh.cheng 2019-10-18 9:53 ` Viresh Kumar 2019-10-18 9:53 ` Viresh Kumar 2019-10-18 9:53 ` Viresh Kumar 2019-08-13 13:31 ` Andrew-sh.Cheng [this message] 2019-08-13 13:31 ` [v4, 2/8] cpufreq: mediatek: add clock enable for intermediate clock Andrew-sh.Cheng 2019-08-19 9:50 ` Viresh Kumar 2019-08-19 9:50 ` Viresh Kumar 2019-08-13 13:31 ` [v4, 4/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-13 13:31 ` [v4, 5/8] devfreq: add mediatek " Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-13 13:31 ` [v4, 6/8] PM / OPP: Support adjusting OPP voltages at runtime Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng 2019-08-19 11:18 ` Viresh Kumar 2019-08-19 11:18 ` Viresh Kumar 2019-11-01 8:08 ` Roger Lu 2019-11-01 8:08 ` Roger Lu 2019-11-01 8:08 ` Roger Lu 2019-11-05 6:56 ` Viresh Kumar 2019-11-05 6:56 ` Viresh Kumar 2019-11-05 6:56 ` Viresh Kumar 2019-08-22 13:51 ` Matthias Brugger 2019-08-22 13:51 ` Matthias Brugger 2019-08-13 13:31 ` [v4, 8/8] devfreq: mediatek: cci devfreq register opp notification for SVS support Andrew-sh.Cheng 2019-08-13 13:31 ` Andrew-sh.Cheng
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