From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Date: Sun, 18 Aug 2019 22:11:58 -0700 [thread overview] Message-ID: <1566191521-7820-26-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com> This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 5 +++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8f16028..d66a7e8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,6 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -44,6 +45,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_otp.h" #include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" @@ -66,10 +68,12 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; +#define SIFIVE_OTP_SERIAL 1 #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, @@ -503,6 +507,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); + sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL); for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 9acb69e..0362121 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Date: Sun, 18 Aug 2019 22:11:58 -0700 [thread overview] Message-ID: <1566191521-7820-26-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com> This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 5 +++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8f16028..d66a7e8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,6 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -44,6 +45,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_otp.h" #include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" @@ -66,10 +68,12 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, }; +#define SIFIVE_OTP_SERIAL 1 #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, @@ -503,6 +507,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); + sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL); for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 9acb69e..0362121 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM }; -- 2.7.4
next prev parent reply other threads:[~2019-08-19 5:23 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-19 5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 20:08 ` [Qemu-devel] " Alistair Francis 2019-08-19 20:08 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-22 22:40 ` [Qemu-devel] " Alistair Francis 2019-08-22 22:40 ` [Qemu-riscv] " Alistair Francis 2019-08-23 1:57 ` Bin Meng 2019-08-23 1:57 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 20:21 ` [Qemu-devel] " Alistair Francis 2019-08-19 20:21 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 20:22 ` [Qemu-devel] " Alistair Francis 2019-08-19 20:22 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-20 18:26 ` [Qemu-devel] " Alistair Francis 2019-08-20 18:26 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-22 22:41 ` [Qemu-devel] " Alistair Francis 2019-08-22 22:41 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:11 ` Bin Meng [this message] 2019-08-19 5:11 ` [Qemu-riscv] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng 2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng 2019-08-19 5:11 ` [Qemu-riscv] " Bin Meng 2019-08-19 5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng 2019-08-19 5:12 ` [Qemu-riscv] " Bin Meng 2019-08-22 22:39 ` [Qemu-devel] " Alistair Francis 2019-08-22 22:39 ` [Qemu-riscv] " Alistair Francis 2019-08-19 5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng 2019-08-19 5:12 ` [Qemu-riscv] " Bin Meng
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