From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-devel] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Date: Sat, 31 Aug 2019 19:53:07 -0700 [thread overview] Message-ID: <1567306391-2682-27-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1567306391-2682-1-git-send-email-bmeng.cn@gmail.com> This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v7: None Changes in v6: None Changes in v5: - change to use defines instead of enums - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_otp - creating a 32-bit val variable and using that instead of casting everywhere in sifive_u_otp_write() - move all register initialization to sifive_u_otp_reset() function - drop sifive_u_otp_create() Changes in v4: - prefix all macros/variables/functions with SIFIVE_U/sifive_u in the sifive_u_otp driver Changes in v3: None Changes in v2: None hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 190 ++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 80 +++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd5..fc3c6dd 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000..7d65a85 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,190 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + + switch (addr) { + case SIFIVE_U_OTP_PA: + return s->pa; + case SIFIVE_U_OTP_PAIO: + return s->paio; + case SIFIVE_U_OTP_PAS: + return s->pas; + case SIFIVE_U_OTP_PCE: + return s->pce; + case SIFIVE_U_OTP_PCLK: + return s->pclk; + case SIFIVE_U_OTP_PDIN: + return s->pdin; + case SIFIVE_U_OTP_PDOUT: + if ((s->pce & SIFIVE_U_OTP_PCE_EN) && + (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_U_OTP_PDSTB: + return s->pdstb; + case SIFIVE_U_OTP_PPROG: + return s->pprog; + case SIFIVE_U_OTP_PTC: + return s->ptc; + case SIFIVE_U_OTP_PTM: + return s->ptm; + case SIFIVE_U_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_U_OTP_PTR: + return s->ptr; + case SIFIVE_U_OTP_PTRIM: + return s->ptrim; + case SIFIVE_U_OTP_PWE: + return s->pwe; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n", + __func__, (int)addr); + return 0; +} + +static void sifive_u_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_OTP_PA: + s->pa = val32 & SIFIVE_U_OTP_PA_MASK; + break; + case SIFIVE_U_OTP_PAIO: + s->paio = val32; + break; + case SIFIVE_U_OTP_PAS: + s->pas = val32; + break; + case SIFIVE_U_OTP_PCE: + s->pce = val32; + break; + case SIFIVE_U_OTP_PCLK: + s->pclk = val32; + break; + case SIFIVE_U_OTP_PDIN: + s->pdin = val32; + break; + case SIFIVE_U_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_U_OTP_PDSTB: + s->pdstb = val32; + break; + case SIFIVE_U_OTP_PPROG: + s->pprog = val32; + break; + case SIFIVE_U_OTP_PTC: + s->ptc = val32; + break; + case SIFIVE_U_OTP_PTM: + s->ptm = val32; + break; + case SIFIVE_U_OTP_PTM_REP: + s->ptm_rep = val32; + break; + case SIFIVE_U_OTP_PTR: + s->ptr = val32; + break; + case SIFIVE_U_OTP_PTRIM: + s->ptrim = val32; + break; + case SIFIVE_U_OTP_PWE: + s->pwe = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_u_otp_ops = { + .read = sifive_u_otp_read, + .write = sifive_u_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_u_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_u_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_otp_reset(DeviceState *dev) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_u_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_u_otp_properties; + dc->realize = sifive_u_otp_realize; + dc->reset = sifive_u_otp_reset; +} + +static const TypeInfo sifive_u_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUOTPState), + .class_init = sifive_u_otp_class_init, +}; + +static void sifive_u_otp_register_types(void) +{ + type_register_static(&sifive_u_otp_info); +} + +type_init(sifive_u_otp_register_types) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000..6392975 --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Date: Sat, 31 Aug 2019 19:53:07 -0700 [thread overview] Message-ID: <1567306391-2682-27-git-send-email-bmeng.cn@gmail.com> (raw) In-Reply-To: <1567306391-2682-1-git-send-email-bmeng.cn@gmail.com> This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v7: None Changes in v6: None Changes in v5: - change to use defines instead of enums - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_otp - creating a 32-bit val variable and using that instead of casting everywhere in sifive_u_otp_write() - move all register initialization to sifive_u_otp_reset() function - drop sifive_u_otp_create() Changes in v4: - prefix all macros/variables/functions with SIFIVE_U/sifive_u in the sifive_u_otp driver Changes in v3: None Changes in v2: None hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_otp.c | 190 ++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_u_otp.h | 80 +++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 hw/riscv/sifive_u_otp.c create mode 100644 include/hw/riscv/sifive_u_otp.h diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index b95bbd5..fc3c6dd 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000..7d65a85 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,190 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + + switch (addr) { + case SIFIVE_U_OTP_PA: + return s->pa; + case SIFIVE_U_OTP_PAIO: + return s->paio; + case SIFIVE_U_OTP_PAS: + return s->pas; + case SIFIVE_U_OTP_PCE: + return s->pce; + case SIFIVE_U_OTP_PCLK: + return s->pclk; + case SIFIVE_U_OTP_PDIN: + return s->pdin; + case SIFIVE_U_OTP_PDOUT: + if ((s->pce & SIFIVE_U_OTP_PCE_EN) && + (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_U_OTP_PDSTB: + return s->pdstb; + case SIFIVE_U_OTP_PPROG: + return s->pprog; + case SIFIVE_U_OTP_PTC: + return s->ptc; + case SIFIVE_U_OTP_PTM: + return s->ptm; + case SIFIVE_U_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_U_OTP_PTR: + return s->ptr; + case SIFIVE_U_OTP_PTRIM: + return s->ptrim; + case SIFIVE_U_OTP_PWE: + return s->pwe; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n", + __func__, (int)addr); + return 0; +} + +static void sifive_u_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_OTP_PA: + s->pa = val32 & SIFIVE_U_OTP_PA_MASK; + break; + case SIFIVE_U_OTP_PAIO: + s->paio = val32; + break; + case SIFIVE_U_OTP_PAS: + s->pas = val32; + break; + case SIFIVE_U_OTP_PCE: + s->pce = val32; + break; + case SIFIVE_U_OTP_PCLK: + s->pclk = val32; + break; + case SIFIVE_U_OTP_PDIN: + s->pdin = val32; + break; + case SIFIVE_U_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_U_OTP_PDSTB: + s->pdstb = val32; + break; + case SIFIVE_U_OTP_PPROG: + s->pprog = val32; + break; + case SIFIVE_U_OTP_PTC: + s->ptc = val32; + break; + case SIFIVE_U_OTP_PTM: + s->ptm = val32; + break; + case SIFIVE_U_OTP_PTM_REP: + s->ptm_rep = val32; + break; + case SIFIVE_U_OTP_PTR: + s->ptr = val32; + break; + case SIFIVE_U_OTP_PTRIM: + s->ptrim = val32; + break; + case SIFIVE_U_OTP_PWE: + s->pwe = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_u_otp_ops = { + .read = sifive_u_otp_read, + .write = sifive_u_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_u_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_u_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_otp_reset(DeviceState *dev) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_u_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_u_otp_properties; + dc->realize = sifive_u_otp_realize; + dc->reset = sifive_u_otp_reset; +} + +static const TypeInfo sifive_u_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUOTPState), + .class_init = sifive_u_otp_class_init, +}; + +static void sifive_u_otp_register_types(void) +{ + type_register_static(&sifive_u_otp_info); +} + +type_init(sifive_u_otp_register_types) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000..6392975 --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ -- 2.7.4
next prev parent reply other threads:[~2019-09-01 3:16 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-09-01 2:52 [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 04/30] riscv: hw: Change create_fdt() to return void Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-03 23:09 ` [Qemu-devel] " Alistair Francis 2019-09-03 23:09 ` [Qemu-riscv] " Alistair Francis 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng 2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` Bin Meng [this message] 2019-09-01 2:53 ` [Qemu-riscv] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng 2019-09-04 16:37 ` [Qemu-devel] " Alistair Francis 2019-09-04 16:37 ` [Qemu-riscv] " Alistair Francis 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng 2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng 2019-09-04 19:49 ` [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis 2019-09-04 19:49 ` [Qemu-riscv] " Alistair Francis 2019-09-05 15:25 ` Bin Meng 2019-09-05 15:25 ` [Qemu-riscv] " Bin Meng 2019-09-05 19:00 ` Palmer Dabbelt 2019-09-05 19:00 ` [Qemu-riscv] " Palmer Dabbelt 2019-09-06 0:32 ` Bin Meng 2019-09-06 0:32 ` [Qemu-riscv] " Bin Meng
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1567306391-2682-27-git-send-email-bmeng.cn@gmail.com \ --to=bmeng.cn@gmail.com \ --cc=Alistair.Francis@wdc.com \ --cc=palmer@sifive.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.