From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images
Date: Sat, 31 Aug 2019 19:52:48 -0700 [thread overview]
Message-ID: <1567306391-2682-8-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1567306391-2682-1-git-send-email-bmeng.cn@gmail.com>
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- new patch to remove executable attribute of opensbi images
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin
3 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin
diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
old mode 100755
new mode 100644
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-riscv] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images
Date: Sat, 31 Aug 2019 19:52:48 -0700 [thread overview]
Message-ID: <1567306391-2682-8-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1567306391-2682-1-git-send-email-bmeng.cn@gmail.com>
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- new patch to remove executable attribute of opensbi images
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin
3 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin
diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
old mode 100755
new mode 100644
--
2.7.4
next prev parent reply other threads:[~2019-09-01 2:59 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-01 2:52 [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` Bin Meng [this message]
2019-09-01 2:52 ` [Qemu-riscv] [PATCH v7 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-03 23:09 ` [Qemu-devel] " Alistair Francis
2019-09-03 23:09 ` [Qemu-riscv] " Alistair Francis
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 16/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:52 ` [Qemu-devel] [PATCH v7 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-09-01 2:52 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-04 16:37 ` [Qemu-devel] " Alistair Francis
2019-09-04 16:37 ` [Qemu-riscv] " Alistair Francis
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-01 2:53 ` [Qemu-devel] [PATCH v7 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
2019-09-01 2:53 ` [Qemu-riscv] " Bin Meng
2019-09-04 19:49 ` [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis
2019-09-04 19:49 ` [Qemu-riscv] " Alistair Francis
2019-09-05 15:25 ` Bin Meng
2019-09-05 15:25 ` [Qemu-riscv] " Bin Meng
2019-09-05 19:00 ` Palmer Dabbelt
2019-09-05 19:00 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-06 0:32 ` Bin Meng
2019-09-06 0:32 ` [Qemu-riscv] " Bin Meng
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