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From: <Eugen.Hristev@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<alexandre.belloni@bootlin.com>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <Nicolas.Ferre@microchip.com>, <Eugen.Hristev@microchip.com>
Subject: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date: Wed, 11 Sep 2019 06:39:20 +0000	[thread overview]
Message-ID: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com> (raw)

From: Eugen Hristev <eugen.hristev@microchip.com>

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
 drivers/clk/at91/sama5d2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 6509d09..0de1108 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
 };
 
 static const struct clk_pll_characteristics plla_characteristics = {
-	.input = { .min = 12000000, .max = 12000000 },
+	.input = { .min = 12000000, .max = 24000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
 	.icpll = plla_icpll,
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: <Eugen.Hristev@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<alexandre.belloni@bootlin.com>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: Eugen.Hristev@microchip.com
Subject: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date: Wed, 11 Sep 2019 06:39:20 +0000	[thread overview]
Message-ID: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com> (raw)

From: Eugen Hristev <eugen.hristev@microchip.com>

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
 drivers/clk/at91/sama5d2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 6509d09..0de1108 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
 };
 
 static const struct clk_pll_characteristics plla_characteristics = {
-	.input = { .min = 12000000, .max = 12000000 },
+	.input = { .min = 12000000, .max = 24000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
 	.icpll = plla_icpll,
-- 
2.7.4


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             reply	other threads:[~2019-09-11  6:39 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-11  6:39 Eugen.Hristev [this message]
2019-09-11  6:39 ` [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Eugen.Hristev
2019-09-11  7:03 ` Nicolas.Ferre
2019-09-11  7:03   ` Nicolas.Ferre
2019-09-12 11:06 ` Alexander Dahl
2019-09-12 11:06   ` Alexander Dahl
2019-09-12 11:28   ` Eugen.Hristev
2019-09-12 11:28     ` Eugen.Hristev
2019-09-16 19:52 ` Stephen Boyd
2019-09-16 19:52   ` Stephen Boyd
2019-09-17  5:59   ` Eugen.Hristev
2019-09-17  5:59     ` Eugen.Hristev
2019-09-18  5:00 ` Stephen Boyd
2019-09-18  5:00   ` Stephen Boyd

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