From: Yash Shah <yash.shah@sifive.com> To: "linus.walleij@linaro.org" <linus.walleij@linaro.org>, "bgolaszewski@baylibre.com" <bgolaszewski@baylibre.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "palmer@dabbelt.com" <palmer@dabbelt.com>, "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com> Cc: "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>, "tglx@linutronix.de" <tglx@linutronix.de>, "jason@lakedaemon.net" <jason@lakedaemon.net>, "maz@kernel.org" <maz@kernel.org>, "bmeng.cn@gmail.com" <bmeng.cn@gmail.com>, "atish.patra@wdc.com" <atish.patra@wdc.com>, Sagar Kadam <sagar.kadam@sifive.com>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Sachin Ghadi <sachin.ghadi@sifive.com>, Yash Shah <yash.shah@sifive.com> Subject: [PATCH v2 2/5] irqchip: sifive: Support hierarchy irq domain Date: Wed, 20 Nov 2019 06:59:28 +0000 [thread overview] Message-ID: <1574233128-28114-3-git-send-email-yash.shah@sifive.com> (raw) In-Reply-To: <1574233128-28114-1-git-send-email-yash.shah@sifive.com> Add support for hierarchy irq domains. This is needed as pre-requisite for gpio-sifive driver. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 30 ++++++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index ccbb897..a398552 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -488,6 +488,7 @@ endmenu config SIFIVE_PLIC bool "SiFive Platform-Level Interrupt Controller" depends on RISCV + select IRQ_DOMAIN_HIERARCHY help This enables support for the PLIC chip found in SiFive (and potentially other) RISC-V systems. The PLIC controls devices diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 7d0a12f..750e366 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -154,15 +154,37 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq); - irq_set_chip_data(irq, NULL); + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, + handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); return 0; } +static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + ret = plic_irqdomain_map(domain, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + static const struct irq_domain_ops plic_irqdomain_ops = { - .map = plic_irqdomain_map, - .xlate = irq_domain_xlate_onecell, + .translate = irq_domain_translate_onecell, + .alloc = plic_irq_domain_alloc, + .free = irq_domain_free_irqs_top, }; static struct irq_domain *plic_irqdomain; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Yash Shah <yash.shah@sifive.com> To: "linus.walleij@linaro.org" <linus.walleij@linaro.org>, "bgolaszewski@baylibre.com" <bgolaszewski@baylibre.com>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "mark.rutland@arm.com" <mark.rutland@arm.com>, "palmer@dabbelt.com" <palmer@dabbelt.com>, "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com> Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>, "jason@lakedaemon.net" <jason@lakedaemon.net>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>, "maz@kernel.org" <maz@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "atish.patra@wdc.com" <atish.patra@wdc.com>, Yash Shah <yash.shah@sifive.com>, Sagar Kadam <sagar.kadam@sifive.com>, "tglx@linutronix.de" <tglx@linutronix.de>, "bmeng.cn@gmail.com" <bmeng.cn@gmail.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, Sachin Ghadi <sachin.ghadi@sifive.com> Subject: [PATCH v2 2/5] irqchip: sifive: Support hierarchy irq domain Date: Wed, 20 Nov 2019 06:59:28 +0000 [thread overview] Message-ID: <1574233128-28114-3-git-send-email-yash.shah@sifive.com> (raw) In-Reply-To: <1574233128-28114-1-git-send-email-yash.shah@sifive.com> Add support for hierarchy irq domains. This is needed as pre-requisite for gpio-sifive driver. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 30 ++++++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index ccbb897..a398552 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -488,6 +488,7 @@ endmenu config SIFIVE_PLIC bool "SiFive Platform-Level Interrupt Controller" depends on RISCV + select IRQ_DOMAIN_HIERARCHY help This enables support for the PLIC chip found in SiFive (and potentially other) RISC-V systems. The PLIC controls devices diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 7d0a12f..750e366 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -154,15 +154,37 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq); - irq_set_chip_data(irq, NULL); + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, + handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); return 0; } +static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + ret = plic_irqdomain_map(domain, virq + i, hwirq + i); + if (ret) + return ret; + } + + return 0; +} + static const struct irq_domain_ops plic_irqdomain_ops = { - .map = plic_irqdomain_map, - .xlate = irq_domain_xlate_onecell, + .translate = irq_domain_translate_onecell, + .alloc = plic_irq_domain_alloc, + .free = irq_domain_free_irqs_top, }; static struct irq_domain *plic_irqdomain; -- 2.7.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-11-20 6:59 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-20 6:59 [PATCH v2 0/5] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah 2019-11-20 6:59 ` Yash Shah 2019-11-20 6:59 ` [PATCH v2 1/5] genirq: introduce irq_domain_translate_onecell Yash Shah 2019-11-20 6:59 ` Yash Shah 2019-11-20 9:34 ` Thomas Gleixner 2019-11-20 9:34 ` Thomas Gleixner 2019-11-20 10:24 ` Marc Zyngier 2019-11-20 10:24 ` Marc Zyngier 2019-11-20 10:48 ` Thomas Gleixner 2019-11-20 10:48 ` Thomas Gleixner 2019-11-20 10:38 ` Marc Zyngier 2019-11-20 10:38 ` Marc Zyngier 2019-11-21 8:35 ` Yash Shah 2019-11-21 8:35 ` Yash Shah 2019-11-21 8:55 ` Yash Shah 2019-11-21 8:55 ` Yash Shah 2019-11-21 9:20 ` Marc Zyngier 2019-11-21 9:20 ` Marc Zyngier 2019-11-20 6:59 ` Yash Shah [this message] 2019-11-20 6:59 ` [PATCH v2 2/5] irqchip: sifive: Support hierarchy irq domain Yash Shah 2019-11-22 10:17 ` Marc Zyngier 2019-11-22 10:17 ` Marc Zyngier 2019-11-20 6:59 ` [PATCH v2 3/5] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah 2019-11-20 6:59 ` Yash Shah 2019-11-20 6:59 ` [PATCH v2 4/5] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah 2019-11-20 6:59 ` Yash Shah 2019-11-20 10:01 ` Bartosz Golaszewski 2019-11-20 10:01 ` Bartosz Golaszewski 2019-11-21 8:32 ` Yash Shah 2019-11-21 8:32 ` Yash Shah 2019-11-20 6:59 ` [PATCH v2 5/5] riscv: dts: Add DT support for SiFive FU540 GPIO driver Yash Shah 2019-11-20 6:59 ` Yash Shah 2019-11-20 9:14 ` Andreas Schwab 2019-11-20 9:14 ` Andreas Schwab 2019-11-21 8:26 ` Yash Shah 2019-11-21 8:26 ` Yash Shah
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