From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
To: <tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
<hpa@zytor.com>, <x86@kernel.org>, <luto@kernel.org>,
<pawan.kumar.gupta@linux.intel.com>, <peterz@infradead.org>,
<fenghua.yu@intel.com>, <vineela.tummalapalli@intel.com>,
<linux-kernel@vger.kernel.org>
Cc: <DavidWang@zhaoxin.com>, <CooperYan@zhaoxin.com>,
<QiyuanWang@zhaoxin.com>, <HerryYang@zhaoxin.com>
Subject: [PATCH v1 1/2] x86/speculation/spectre_v2: Exclude Zhaoxin CPUs from SPECTRE_V2
Date: Fri, 17 Jan 2020 10:24:31 +0800 [thread overview]
Message-ID: <1579227872-26972-2-git-send-email-TonyWWang-oc@zhaoxin.com> (raw)
In-Reply-To: <1579227872-26972-1-git-send-email-TonyWWang-oc@zhaoxin.com>
New Zhaoxin family 7 CPUs are not affected by SPECTRE_V2. So create
a separate cpu_vuln_whitelist flag bit NO_SPECTRE_V2 and add these
CPUs to the cpu vulnerability whitelist.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
arch/x86/kernel/cpu/common.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 2e4d902..6048bd3 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1023,6 +1023,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
#define MSBDS_ONLY BIT(5)
#define NO_SWAPGS BIT(6)
#define NO_ITLB_MULTIHIT BIT(7)
+#define NO_SPECTRE_V2 BIT(8)
#define VULNWL(_vendor, _family, _model, _whitelist) \
{ X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
@@ -1084,6 +1085,10 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
+
+ /* Zhaoxin Family 7 */
+ VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2),
+ VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2),
{}
};
@@ -1116,7 +1121,9 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
return;
setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
- setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+
+ if (!cpu_matches(NO_SPECTRE_V2))
+ setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
!cpu_has(c, X86_FEATURE_AMD_SSB_NO))
--
2.7.4
next prev parent reply other threads:[~2020-01-17 2:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-17 2:24 [PATCH v1 0/2] x86/bugs: Exclude Zhaoxin family 7 CPUs Tony W Wang-oc
2020-01-17 2:24 ` Tony W Wang-oc [this message]
2020-01-17 18:19 ` [tip: x86/pti] x86/speculation/spectre_v2: Exclude Zhaoxin CPUs from SPECTRE_V2 tip-bot2 for Tony W Wang-oc
2020-01-17 2:24 ` [PATCH v1 2/2] x86/speculation/swapgs: Exclude Zhaoxin CPUs from SWAPGS Tony W Wang-oc
2020-01-17 18:19 ` [tip: x86/pti] x86/speculation/swapgs: Exclude Zhaoxin CPUs from SWAPGS vulnerability tip-bot2 for Tony W Wang-oc
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