From: Anson Huang <Anson.Huang@nxp.com> To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, devicetree@vger.kernel.org, u.kleine-koenig@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 RESEND 3/7] ARM: dts: imx6sx-nitrogen6sx: Use new pin names with DCE/DTE for UART pins Date: Mon, 17 Feb 2020 19:13:37 +0800 [thread overview] Message-ID: <1581938021-16259-3-git-send-email-Anson.Huang@nxp.com> (raw) In-Reply-To: <1581938021-16259-1-git-send-email-Anson.Huang@nxp.com> Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> --- No change. --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 832b5c5..d84ea69 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -484,31 +484,31 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 >; }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anson Huang <Anson.Huang@nxp.com> To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, devicetree@vger.kernel.org, u.kleine-koenig@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 RESEND 3/7] ARM: dts: imx6sx-nitrogen6sx: Use new pin names with DCE/DTE for UART pins Date: Mon, 17 Feb 2020 19:13:37 +0800 [thread overview] Message-ID: <1581938021-16259-3-git-send-email-Anson.Huang@nxp.com> (raw) In-Reply-To: <1581938021-16259-1-git-send-email-Anson.Huang@nxp.com> Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> --- No change. --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 832b5c5..d84ea69 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -484,31 +484,31 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 >; }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-17 11:19 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-17 11:13 [PATCH V3 RESEND 1/7] ARM: dts: imx6sx: Improve UART pins macro defines Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-17 11:13 ` [PATCH V3 RESEND 2/7] ARM: dts: imx6sx: Add missing UART RTS/CTS pins mux Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-19 3:03 ` Rob Herring 2020-02-19 3:03 ` Rob Herring 2020-02-17 11:13 ` Anson Huang [this message] 2020-02-17 11:13 ` [PATCH V3 RESEND 3/7] ARM: dts: imx6sx-nitrogen6sx: Use new pin names with DCE/DTE for UART pins Anson Huang 2020-02-17 11:13 ` [PATCH V3 RESEND 4/7] ARM: dts: imx6sx-sabreauto: " Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-17 11:13 ` [PATCH V3 RESEND 5/7] ARM: dts: imx6sx-sdb: " Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-17 11:13 ` [PATCH V3 RESEND 6/7] ARM: dts: imx6sx-softing-vining-2000: " Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-17 11:13 ` [PATCH V3 RESEND 7/7] ARM: dts: imx6sx-udoo-neo: " Anson Huang 2020-02-17 11:13 ` Anson Huang 2020-02-18 9:43 ` [PATCH V3 RESEND 1/7] ARM: dts: imx6sx: Improve UART pins macro defines Shawn Guo 2020-02-18 9:43 ` Shawn Guo 2020-02-19 3:03 ` Rob Herring 2020-02-19 3:03 ` Rob Herring
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