From: Srinivas Neeli <srinivas.neeli@xilinx.com> To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@xilinx.com Subject: [PATCH V3 6/7] gpio: zynq: Add pmc gpio support Date: Mon, 17 Feb 2020 18:03:12 +0530 [thread overview] Message-ID: <1581942793-19468-7-git-send-email-srinivas.neeli@xilinx.com> (raw) In-Reply-To: <1581942793-19468-1-git-send-email-srinivas.neeli@xilinx.com> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Add PMC gpio support. Only bank 0,1, 3 and 4 are connected to the multiplexed Input output pins. Bank 0 and 1 to mio and bank 3 and 4 to extended multiplexed input output pins. Versal devices are the industry's first adaptive compute acceleration platforms. https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf On the Versal platform, we are using two customized GPIO controllers(IP) which were used in Zynq/ZynqMp platform. One of them present in the Platform Management Controller(PMC) block and other in Processing System(PS) block. In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only Bank 0 & 3 are enabled. You can find more details of GPIO IP in ZynqMP TRM General Purpose I/O(Chapter-27). https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- drivers/gpio/gpio-zynq.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index b6261a3aec55..2ddb59b242e7 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -23,6 +23,7 @@ #define ZYNQ_GPIO_MAX_BANK 4 #define ZYNQMP_GPIO_MAX_BANK 6 #define VERSAL_GPIO_MAX_BANK 4 +#define PMC_GPIO_MAX_BANK 5 #define VERSAL_UNUSED_BANKS 2 #define ZYNQ_GPIO_BANK0_NGPIO 32 @@ -815,6 +816,20 @@ static const struct zynq_platform_data versal_gpio_def = { .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ }; +static const struct zynq_platform_data pmc_gpio_def = { + .label = "pmc_gpio", + .ngpio = 116, + .max_bank = PMC_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ + .bank_min[1] = 26, + .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */ + .bank_min[3] = 52, + .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */ + .bank_min[4] = 84, + .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */ +}; + static const struct zynq_platform_data zynqmp_gpio_def = { .label = "zynqmp_gpio", .quirks = GPIO_QUIRK_DATA_RO_BUG, @@ -853,6 +868,7 @@ static const struct of_device_id zynq_gpio_of_match[] = { { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, + { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def }, { /* end of table */ } }; MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Srinivas Neeli <srinivas.neeli@xilinx.com> To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Subject: [PATCH V3 6/7] gpio: zynq: Add pmc gpio support Date: Mon, 17 Feb 2020 18:03:12 +0530 [thread overview] Message-ID: <1581942793-19468-7-git-send-email-srinivas.neeli@xilinx.com> (raw) In-Reply-To: <1581942793-19468-1-git-send-email-srinivas.neeli@xilinx.com> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Add PMC gpio support. Only bank 0,1, 3 and 4 are connected to the multiplexed Input output pins. Bank 0 and 1 to mio and bank 3 and 4 to extended multiplexed input output pins. Versal devices are the industry's first adaptive compute acceleration platforms. https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf On the Versal platform, we are using two customized GPIO controllers(IP) which were used in Zynq/ZynqMp platform. One of them present in the Platform Management Controller(PMC) block and other in Processing System(PS) block. In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only Bank 0 & 3 are enabled. You can find more details of GPIO IP in ZynqMP TRM General Purpose I/O(Chapter-27). https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- drivers/gpio/gpio-zynq.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index b6261a3aec55..2ddb59b242e7 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -23,6 +23,7 @@ #define ZYNQ_GPIO_MAX_BANK 4 #define ZYNQMP_GPIO_MAX_BANK 6 #define VERSAL_GPIO_MAX_BANK 4 +#define PMC_GPIO_MAX_BANK 5 #define VERSAL_UNUSED_BANKS 2 #define ZYNQ_GPIO_BANK0_NGPIO 32 @@ -815,6 +816,20 @@ static const struct zynq_platform_data versal_gpio_def = { .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ }; +static const struct zynq_platform_data pmc_gpio_def = { + .label = "pmc_gpio", + .ngpio = 116, + .max_bank = PMC_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ + .bank_min[1] = 26, + .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */ + .bank_min[3] = 52, + .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */ + .bank_min[4] = 84, + .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */ +}; + static const struct zynq_platform_data zynqmp_gpio_def = { .label = "zynqmp_gpio", .quirks = GPIO_QUIRK_DATA_RO_BUG, @@ -853,6 +868,7 @@ static const struct of_device_id zynq_gpio_of_match[] = { { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, + { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def }, { /* end of table */ } }; MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-17 12:34 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-17 12:33 [PATCH V3 0/7] gpio: zynq: Update on gpio-zynq driver Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-17 12:33 ` [PATCH V3 1/7] gpio: zynq: protect direction in/out with a spinlock Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-17 12:33 ` [PATCH V3 2/7] dt-bindings: gpio: Add binding for Versal gpio Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-20 10:25 ` Bartosz Golaszewski 2020-02-20 10:25 ` Bartosz Golaszewski 2020-02-17 12:33 ` [PATCH V3 3/7] devicetree-binding: Add pmc gpio node Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-20 10:26 ` Bartosz Golaszewski 2020-02-20 10:26 ` Bartosz Golaszewski 2020-02-17 12:33 ` [PATCH V3 4/7] gpio: zynq: Add Versal support Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-17 12:33 ` [PATCH V3 5/7] gpio: zynq: Disable the irq if it is not a wakeup source Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli [this message] 2020-02-17 12:33 ` [PATCH V3 6/7] gpio: zynq: Add pmc gpio support Srinivas Neeli 2020-02-17 12:33 ` [PATCH V3 7/7] gpio: zynq: Remove error prints in EPROBE_DEFER Srinivas Neeli 2020-02-17 12:33 ` Srinivas Neeli 2020-02-20 10:28 ` [PATCH V3 0/7] gpio: zynq: Update on gpio-zynq driver Bartosz Golaszewski 2020-02-20 10:28 ` Bartosz Golaszewski 2020-02-21 13:45 ` Linus Walleij 2020-02-21 13:45 ` Linus Walleij
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