From: peng.fan@nxp.com To: shawnguo@kernel.org, s.hauer@pengutronix.de, sboyd@kernel.org, robh+dt@kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, Anson.Huang@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, abel.vesa@nxp.com, Peng Fan <peng.fan@nxp.com> Subject: [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM core clk Date: Wed, 19 Feb 2020 15:59:50 +0800 [thread overview] Message-ID: <1582099197-20327-8-git-send-email-peng.fan@nxp.com> (raw) In-Reply-To: <1582099197-20327-1-git-send-email-peng.fan@nxp.com> From: Peng Fan <peng.fan@nxp.com> ARM clk could only source from divcore or hsrun_divcore. However when ARM core is running normaly, whether divcore or hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when configure the rate. So add CORE and HSRUN_CORE virtual clk to make it easy to configure the clk using imx_clk_hw_cpu API. Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk, prograting it the parent with CLK_SET_RATE_PARENT will finally set the SPLL_PFD0 clk. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-imx7ulp.c | 6 ++++-- include/dt-bindings/clock/imx7ulp-clock.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 3710aa0dee9b..634c0b6636b0 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -29,7 +29,7 @@ static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dum static const char * const nic_sels[] = { "firc", "ddr_clk", }; static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; -static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", }; +static const char * const arm_sels[] = { "core", "dummy", "dummy", "hsrun_core", }; /* used by sosc/sirc/firc/ddr/spll/apll dividers */ static const struct clk_div_table ulp_div_table[] = { @@ -121,7 +121,9 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) hws[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); hws[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); + hws[IMX7ULP_CLK_CORE] = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); hws[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); + hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, 0, ulp_div_table, &imx_ccm_lock); @@ -270,7 +272,7 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np) base = of_iomap(np, 0); WARN_ON(!base); - hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL); + hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT); imx_check_clk_hws(hws, clk_data->num); diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 38145bdcd975..b58370d146e2 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -58,7 +58,10 @@ #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_CORE 46 +#define IMX7ULP_CLK_HSRUN_CORE 47 + +#define IMX7ULP_CLK_SCG1_END 48 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 -- 2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: peng.fan@nxp.com To: shawnguo@kernel.org, s.hauer@pengutronix.de, sboyd@kernel.org, robh+dt@kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net Cc: Peng Fan <peng.fan@nxp.com>, abel.vesa@nxp.com, Anson.Huang@nxp.com, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM core clk Date: Wed, 19 Feb 2020 15:59:50 +0800 [thread overview] Message-ID: <1582099197-20327-8-git-send-email-peng.fan@nxp.com> (raw) In-Reply-To: <1582099197-20327-1-git-send-email-peng.fan@nxp.com> From: Peng Fan <peng.fan@nxp.com> ARM clk could only source from divcore or hsrun_divcore. However when ARM core is running normaly, whether divcore or hwrun_divcore will finally source from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE, so we need to disable SPLL_PFD0, when configure the rate. So add CORE and HSRUN_CORE virtual clk to make it easy to configure the clk using imx_clk_hw_cpu API. Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk, prograting it the parent with CLK_SET_RATE_PARENT will finally set the SPLL_PFD0 clk. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-imx7ulp.c | 6 ++++-- include/dt-bindings/clock/imx7ulp-clock.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 3710aa0dee9b..634c0b6636b0 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -29,7 +29,7 @@ static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dum static const char * const nic_sels[] = { "firc", "ddr_clk", }; static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; -static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", }; +static const char * const arm_sels[] = { "core", "dummy", "dummy", "hsrun_core", }; /* used by sosc/sirc/firc/ddr/spll/apll dividers */ static const struct clk_div_table ulp_div_table[] = { @@ -121,7 +121,9 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) hws[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); hws[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); + hws[IMX7ULP_CLK_CORE] = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); hws[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); + hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk); hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, 0, ulp_div_table, &imx_ccm_lock); @@ -270,7 +272,7 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np) base = of_iomap(np, 0); WARN_ON(!base); - hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL); + hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT); imx_check_clk_hws(hws, clk_data->num); diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 38145bdcd975..b58370d146e2 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -58,7 +58,10 @@ #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_CORE 46 +#define IMX7ULP_CLK_HSRUN_CORE 47 + +#define IMX7ULP_CLK_SCG1_END 48 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 -- 2.16.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-19 8:06 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-19 7:59 [PATCH v2 00/14] ARM: imx7ulp: add cpufreq using cpufreq-dt peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 01/14] dt-bindings: fsl: add i.MX7ULP PMC binding doc peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 5:49 ` Shawn Guo 2020-03-10 5:49 ` Shawn Guo 2020-03-10 5:56 ` Peng Fan 2020-03-10 5:56 ` Peng Fan 2020-03-11 7:39 ` Peng Fan 2020-03-11 7:39 ` Peng Fan 2020-03-11 7:39 ` Peng Fan 2020-02-19 7:59 ` [PATCH v2 02/14] ARM: dts: imx7ulp: add pmc node peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 03/14] clk: imx: Fix division by zero warning on pfdv2 peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 5:53 ` Shawn Guo 2020-03-10 5:53 ` Shawn Guo 2020-02-19 7:59 ` [PATCH v2 04/14] clk: imx: pfdv2: switch to use determine_rate peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 6:02 ` Shawn Guo 2020-03-10 6:02 ` Shawn Guo 2020-02-19 7:59 ` [PATCH v2 05/14] clk: imx: pfdv2: determine best parent rate peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 6:04 ` Shawn Guo 2020-03-10 6:04 ` Shawn Guo 2020-02-19 7:59 ` [PATCH v2 06/14] clk: imx: pllv4: use prepare/unprepare peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 6:04 ` Shawn Guo 2020-03-10 6:04 ` Shawn Guo 2020-02-19 7:59 ` peng.fan [this message] 2020-02-19 7:59 ` [PATCH v2 07/14] clk: imx7ulp: make it easy to change ARM core clk peng.fan 2020-03-10 6:09 ` Shawn Guo 2020-03-10 6:09 ` Shawn Guo 2020-03-10 6:19 ` Peng Fan 2020-03-10 6:19 ` Peng Fan 2020-02-19 7:59 ` [PATCH v2 08/14] ARM: imx: imx7ulp: support HSRUN mode peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 09/14] ARM: imx: cpuidle-imx7ulp: Stop mode disallowed when HSRUN peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-10 6:13 ` Shawn Guo 2020-03-10 6:13 ` Shawn Guo 2020-03-10 7:35 ` Peng Fan 2020-03-10 7:35 ` Peng Fan 2020-02-19 7:59 ` [PATCH v2 10/14] cpufreq: dt: Allow platform specific intermediate callbacks peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 9:35 ` Viresh Kumar 2020-02-19 9:35 ` Viresh Kumar 2020-02-19 9:41 ` Peng Fan 2020-02-19 9:41 ` Peng Fan 2020-02-19 9:45 ` Viresh Kumar 2020-02-19 9:45 ` Viresh Kumar 2020-02-19 9:46 ` Viresh Kumar 2020-02-19 9:46 ` Viresh Kumar 2020-02-19 9:55 ` Peng Fan 2020-02-19 9:55 ` Peng Fan 2020-03-12 10:15 ` Viresh Kumar 2020-03-12 10:15 ` Viresh Kumar 2020-02-19 7:59 ` [PATCH v2 11/14] cpufreq: Add i.MX7ULP to cpufreq-dt-platdev blacklist peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 12/14] cpufreq: imx-cpufreq-dt: support i.MX7ULP peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 13/14] ARM: imx7ulp: enable cpufreq peng.fan 2020-02-19 7:59 ` peng.fan 2020-02-19 7:59 ` [PATCH v2 14/14] [Do not Apply] ARM: dts: imx7ulp: add cpu OPP points peng.fan 2020-02-19 7:59 ` peng.fan 2020-03-02 1:40 ` [PATCH v2 00/14] ARM: imx7ulp: add cpufreq using cpufreq-dt Peng Fan 2020-03-02 1:40 ` Peng Fan 2020-03-02 17:48 ` Fabio Estevam 2020-03-02 17:48 ` Fabio Estevam 2020-03-03 1:08 ` Peng Fan 2020-03-03 1:08 ` Peng Fan
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