From: Jolly Shah <jolly.shah@xilinx.com> To: ard.biesheuvel@linaro.org, mingo@kernel.org, gregkh@linuxfoundation.org, matt@codeblueprint.co.uk, sudeep.holla@arm.com, hkallweit1@gmail.com, keescook@chromium.org, dmitry.torokhov@gmail.com, michal.simek@xilinx.com Cc: rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>, Jolly Shah <jolly.shah@xilinx.com> Subject: [PATCH v3 07/24] firmware: xilinx: Remove eemi ops for clock_setdivider Date: Fri, 6 Mar 2020 15:47:15 -0800 [thread overview] Message-ID: <1583538452-1992-8-git-send-email-jolly.shah@xilinx.com> (raw) In-Reply-To: <1583538452-1992-1-git-send-email-jolly.shah@xilinx.com> From: Rajan Vaja <rajan.vaja@xilinx.com> Use direct function call instead of using eemi ops for clock_setdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> --- drivers/clk/zynqmp/divider.c | 3 +-- drivers/clk/zynqmp/pll.c | 4 ++-- drivers/firmware/xilinx/zynqmp.c | 4 ++-- include/linux/firmware/xlnx-zynqmp.h | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e21f4ea..13041cd 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -219,7 +219,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, u32 div_type = divider->div_type; u32 value, div; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { @@ -233,7 +232,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) div = __ffs(div); - ret = eemi_ops->clock_setdivider(clk_id, div); + ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 41f376a..95fad06 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -187,7 +187,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, rate = parent_rate * m; frac = (parent_rate * f) / FRAC_DIV; - ret = eemi_ops->clock_setdivider(clk_id, m); + ret = zynqmp_pm_clock_setdivider(clk_id, m); if (ret == -EUSERS) WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); @@ -201,7 +201,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - ret = eemi_ops->clock_setdivider(clk_id, fbdiv); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 8a0d5af..eb39735 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -405,11 +405,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate); * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider); /** * zynqmp_pm_clock_getdivider() - Get the clock divider for given id @@ -714,7 +715,6 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, } static const struct zynqmp_eemi_ops eemi_ops = { - .clock_setdivider = zynqmp_pm_clock_setdivider, .clock_getdivider = zynqmp_pm_clock_getdivider, .clock_setrate = zynqmp_pm_clock_setrate, .clock_getrate = zynqmp_pm_clock_getrate, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 44c6702..412b32f 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -288,7 +288,6 @@ struct zynqmp_pm_query_data { struct zynqmp_eemi_ops { int (*fpga_load)(const u64 address, const u32 size, const u32 flags); int (*fpga_get_status)(u32 *value); - int (*clock_setdivider)(u32 clock_id, u32 divider); int (*clock_getdivider)(u32 clock_id, u32 *divider); int (*clock_setrate)(u32 clock_id, u64 rate); int (*clock_getrate)(u32 clock_id, u64 *rate); @@ -317,6 +316,7 @@ int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); int zynqmp_pm_clock_enable(u32 clock_id); int zynqmp_pm_clock_disable(u32 clock_id); int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Jolly Shah <jolly.shah@xilinx.com> To: ard.biesheuvel@linaro.org, mingo@kernel.org, gregkh@linuxfoundation.org, matt@codeblueprint.co.uk, sudeep.holla@arm.com, hkallweit1@gmail.com, keescook@chromium.org, dmitry.torokhov@gmail.com, michal.simek@xilinx.com Cc: Jolly Shah <jolly.shah@xilinx.com>, Rajan Vaja <rajan.vaja@xilinx.com>, rajanv@xilinx.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 07/24] firmware: xilinx: Remove eemi ops for clock_setdivider Date: Fri, 6 Mar 2020 15:47:15 -0800 [thread overview] Message-ID: <1583538452-1992-8-git-send-email-jolly.shah@xilinx.com> (raw) In-Reply-To: <1583538452-1992-1-git-send-email-jolly.shah@xilinx.com> From: Rajan Vaja <rajan.vaja@xilinx.com> Use direct function call instead of using eemi ops for clock_setdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> --- drivers/clk/zynqmp/divider.c | 3 +-- drivers/clk/zynqmp/pll.c | 4 ++-- drivers/firmware/xilinx/zynqmp.c | 4 ++-- include/linux/firmware/xlnx-zynqmp.h | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e21f4ea..13041cd 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -219,7 +219,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, u32 div_type = divider->div_type; u32 value, div; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { @@ -233,7 +232,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) div = __ffs(div); - ret = eemi_ops->clock_setdivider(clk_id, div); + ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 41f376a..95fad06 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -187,7 +187,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, rate = parent_rate * m; frac = (parent_rate * f) / FRAC_DIV; - ret = eemi_ops->clock_setdivider(clk_id, m); + ret = zynqmp_pm_clock_setdivider(clk_id, m); if (ret == -EUSERS) WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); @@ -201,7 +201,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - ret = eemi_ops->clock_setdivider(clk_id, fbdiv); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 8a0d5af..eb39735 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -405,11 +405,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate); * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider); /** * zynqmp_pm_clock_getdivider() - Get the clock divider for given id @@ -714,7 +715,6 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, } static const struct zynqmp_eemi_ops eemi_ops = { - .clock_setdivider = zynqmp_pm_clock_setdivider, .clock_getdivider = zynqmp_pm_clock_getdivider, .clock_setrate = zynqmp_pm_clock_setrate, .clock_getrate = zynqmp_pm_clock_getrate, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 44c6702..412b32f 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -288,7 +288,6 @@ struct zynqmp_pm_query_data { struct zynqmp_eemi_ops { int (*fpga_load)(const u64 address, const u32 size, const u32 flags); int (*fpga_get_status)(u32 *value); - int (*clock_setdivider)(u32 clock_id, u32 divider); int (*clock_getdivider)(u32 clock_id, u32 *divider); int (*clock_setrate)(u32 clock_id, u64 rate); int (*clock_getrate)(u32 clock_id, u64 *rate); @@ -317,6 +316,7 @@ int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); int zynqmp_pm_clock_enable(u32 clock_id); int zynqmp_pm_clock_disable(u32 clock_id); int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-06 23:48 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-06 23:47 [PATCH v3 00/24] firmware: xilinx: Add xilinx specific sysfs interface Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 01/24] firmware: xilinx: Remove eemi ops for get_api_version Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 02/24] firmware: xilinx: Remove eemi ops for get_chipid Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 03/24] firmware: xilinx: Remove eemi ops for query_data Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 04/24] firmware: xilinx: Remove eemi ops for clock_enable Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 05/24] firmware: xilinx: Remove eemi ops for clock_disable Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 06/24] firmware: xilinx: Remove eemi ops for clock_getstate Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` Jolly Shah [this message] 2020-03-06 23:47 ` [PATCH v3 07/24] firmware: xilinx: Remove eemi ops for clock_setdivider Jolly Shah 2020-03-06 23:47 ` [PATCH v3 08/24] firmware: xilinx: Remove eemi ops for clock_getdivider Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 09/24] firmware: xilinx: Remove eemi ops for clock set/get rate Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 10/24] firmware: xilinx: Remove eemi ops for clock set/get parent Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 11/24] firmware: xilinx: Use APIs instead of IOCTLs Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 12/24] firmware: xilinx: Remove eemi ops for reset_assert Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 13/24] firmware: xilinx: Remove eemi ops for reset_get_status Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 14/24] firmware: xilinx: Remove eemi ops for init_finalize Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 15/24] firmware: xilinx: Remove eemi ops for set_suspend_mode Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 16/24] firmware: xilinx: Remove eemi ops for request_node Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 17/24] firmware: xilinx: Remove eemi ops for release_node Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 18/24] firmware: xilinx: Remove eemi ops for set_requirement Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 19/24] firmware: xilinx: Remove eemi ops for fpga related APIs Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-06 23:47 ` [PATCH v3 20/24] firmware: xilinx: Add APIs to read/write GGS/PGGS registers Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-18 11:51 ` Greg KH 2020-03-18 11:51 ` Greg KH 2020-03-18 12:41 ` Rajan Vaja 2020-03-18 12:41 ` Rajan Vaja 2020-03-18 12:50 ` Greg KH 2020-03-18 12:50 ` Greg KH 2020-03-06 23:47 ` [PATCH v3 21/24] firmware: xilinx: Add sysfs interface Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-18 11:51 ` Greg KH 2020-03-18 11:51 ` Greg KH 2020-03-06 23:47 ` [PATCH v3 22/24] firmware: xilinx: Add system shutdown API interface Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-18 11:52 ` Greg KH 2020-03-18 11:52 ` Greg KH 2020-03-06 23:47 ` [PATCH v3 23/24] firmware: xilinx: Add sysfs to set shutdown scope Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-18 11:53 ` Greg KH 2020-03-18 11:53 ` Greg KH 2020-03-06 23:47 ` [PATCH v3 24/24] firmware: xilinx: Add sysfs and API to set boot health status Jolly Shah 2020-03-06 23:47 ` Jolly Shah 2020-03-18 11:53 ` Greg KH 2020-03-18 11:53 ` Greg KH 2020-03-18 11:54 ` [PATCH v3 00/24] firmware: xilinx: Add xilinx specific sysfs interface Greg KH 2020-03-18 11:54 ` Greg KH 2020-04-09 19:17 ` Jolly Shah 2020-04-09 19:17 ` Jolly Shah
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