From: Anson Huang <Anson.Huang@nxp.com> To: rui.zhang@intel.com, daniel.lezcano@linaro.org, amit.kucheria@verdurent.com, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, horia.geanta@nxp.com, peng.fan@nxp.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 3/3] arm64: dts: imx8mp: Add thermal zones support Date: Mon, 23 Mar 2020 20:28:24 +0800 [thread overview] Message-ID: <1584966504-21719-3-git-send-email-Anson.Huang@nxp.com> (raw) In-Reply-To: <1584966504-21719-1-git-send-email-Anson.Huang@nxp.com> i.MX8MP has a TMU inside which supports two thermal zones, add support for them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- No change. --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 63 +++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9b1616e..175165b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8mp-pinfunc.h" @@ -43,6 +44,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -53,6 +55,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -63,6 +66,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -73,6 +77,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -127,6 +132,57 @@ method = "smc"; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, @@ -215,6 +271,13 @@ gpio-ranges = <&iomuxc 0 114 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anson Huang <Anson.Huang@nxp.com> To: rui.zhang@intel.com, daniel.lezcano@linaro.org, amit.kucheria@verdurent.com, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, horia.geanta@nxp.com, peng.fan@nxp.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 3/3] arm64: dts: imx8mp: Add thermal zones support Date: Mon, 23 Mar 2020 20:28:24 +0800 [thread overview] Message-ID: <1584966504-21719-3-git-send-email-Anson.Huang@nxp.com> (raw) In-Reply-To: <1584966504-21719-1-git-send-email-Anson.Huang@nxp.com> i.MX8MP has a TMU inside which supports two thermal zones, add support for them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- No change. --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 63 +++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9b1616e..175165b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8mp-pinfunc.h" @@ -43,6 +44,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -53,6 +55,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -63,6 +66,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -73,6 +77,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -127,6 +132,57 @@ method = "smc"; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0x1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, @@ -215,6 +271,13 @@ gpio-ranges = <&iomuxc 0 114 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-23 12:35 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-23 12:28 [PATCH V3 1/3] dt-bindings: thermal: imx8mm-thermal: Add support for i.MX8MP Anson Huang 2020-03-23 12:28 ` Anson Huang 2020-03-23 12:28 ` [PATCH V3 2/3] thermal: imx8mm: Add i.MX8MP support Anson Huang 2020-03-23 12:28 ` Anson Huang 2020-03-23 14:10 ` Daniel Lezcano 2020-03-23 14:10 ` Daniel Lezcano 2020-03-23 14:27 ` Anson Huang 2020-03-23 14:27 ` Anson Huang 2020-03-24 0:52 ` Anson Huang 2020-03-24 0:52 ` Anson Huang 2020-03-23 12:28 ` Anson Huang [this message] 2020-03-23 12:28 ` [PATCH V3 3/3] arm64: dts: imx8mp: Add thermal zones support Anson Huang 2020-04-02 10:40 ` Amit Kucheria 2020-04-02 10:40 ` Amit Kucheria 2020-04-03 3:34 ` Anson Huang 2020-04-03 3:34 ` Anson Huang 2020-04-03 5:45 ` Amit Kucheria 2020-04-03 5:45 ` Amit Kucheria 2020-04-03 6:04 ` Anson Huang 2020-04-03 6:04 ` Anson Huang 2020-04-03 12:26 ` [PATCH V3 1/3] dt-bindings: thermal: imx8mm-thermal: Add support for i.MX8MP Amit Kucheria 2020-04-03 12:26 ` Amit Kucheria 2020-04-03 12:33 ` Anson Huang 2020-04-03 12:33 ` Anson Huang
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