From: Srinath Mannam <srinath.mannam@broadcom.com> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>, Rob Herring <robh+dt@kernel.org>, Andrew Murray <andrew.murray@arm.com>, Mark Rutland <mark.rutland@arm.com>, Andy Shevchenko <andy.shevchenko@gmail.com>, Arnd Bergmann <arnd@arndb.de> Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui <ray.jui@broadcom.com>, Srinath Mannam <srinath.mannam@broadcom.com> Subject: [PATCH v5 5/6] arm: dts: Change PCIe INTx mapping for HR2 Date: Thu, 26 Mar 2020 12:18:45 +0530 [thread overview] Message-ID: <1585205326-25326-6-git-send-email-srinath.mannam@broadcom.com> (raw) In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> From: Ray Jui <ray.jui@broadcom.com> Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> --- arch/arm/boot/dts/bcm-hr2.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 6142c67..80c3add 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -299,8 +299,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -328,6 +331,14 @@ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + }; }; pcie1: pcie@18013000 { @@ -335,8 +346,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -364,5 +378,13 @@ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Srinath Mannam <srinath.mannam@broadcom.com> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>, Rob Herring <robh+dt@kernel.org>, Andrew Murray <andrew.murray@arm.com>, Mark Rutland <mark.rutland@arm.com>, Andy Shevchenko <andy.shevchenko@gmail.com>, Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Srinath Mannam <srinath.mannam@broadcom.com>, linux-kernel@vger.kernel.org, Ray Jui <ray.jui@broadcom.com>, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/6] arm: dts: Change PCIe INTx mapping for HR2 Date: Thu, 26 Mar 2020 12:18:45 +0530 [thread overview] Message-ID: <1585205326-25326-6-git-send-email-srinath.mannam@broadcom.com> (raw) In-Reply-To: <1585205326-25326-1-git-send-email-srinath.mannam@broadcom.com> From: Ray Jui <ray.jui@broadcom.com> Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> --- arch/arm/boot/dts/bcm-hr2.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 6142c67..80c3add 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -299,8 +299,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -328,6 +331,14 @@ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + }; }; pcie1: pcie@18013000 { @@ -335,8 +346,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -364,5 +378,13 @@ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-26 6:49 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-26 6:48 [PATCH v5 0/6] PAXB INTx support with proper model Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam 2020-03-26 6:48 ` [PATCH v5 1/6] dt-bindings: pci: Update iProc PCI binding for INTx support Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam 2020-03-26 12:37 ` Arnd Bergmann 2020-03-26 12:37 ` Arnd Bergmann 2020-03-26 14:22 ` Bjorn Helgaas 2020-03-26 14:22 ` Bjorn Helgaas 2020-03-26 14:51 ` Marc Zyngier 2020-03-26 14:51 ` Marc Zyngier 2020-03-26 6:48 ` [PATCH v5 2/6] PCI: iproc: Add INTx support with better modeling Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam 2020-03-26 12:34 ` Arnd Bergmann 2020-03-26 12:34 ` Arnd Bergmann 2020-03-26 14:37 ` Andy Shevchenko 2020-03-26 14:37 ` Andy Shevchenko 2020-03-26 15:03 ` Marc Zyngier 2020-03-26 15:03 ` Marc Zyngier 2020-03-26 6:48 ` [PATCH v5 3/6] arm: dts: Change PCIe INTx mapping for Cygnus Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam 2020-03-26 6:48 ` [PATCH v5 4/6] arm: dts: Change PCIe INTx mapping for NSP Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam [this message] 2020-03-26 6:48 ` [PATCH v5 5/6] arm: dts: Change PCIe INTx mapping for HR2 Srinath Mannam 2020-03-26 6:48 ` [PATCH v5 6/6] arm64: dts: Change PCIe INTx mapping for NS2 Srinath Mannam 2020-03-26 6:48 ` Srinath Mannam
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