From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, suzuki.poulose@arm.com, Anshuman Khandual <anshuman.khandual@arm.com>, linux-kernel@vger.kernel.org Subject: [PATCH V2 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Date: Tue, 14 Apr 2020 15:18:26 +0530 [thread overview] Message-ID: <1586857710-17154-13-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1586857710-17154-1-git-send-email-anshuman.khandual@arm.com> Enable EVC, FGT, EXS, TGRAN4_2, TGRAN64_2 and TGRAN16_2 features bits in ID_AA64MMFR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/include/asm/sysreg.h | 13 +++++++++++++ arch/arm64/kernel/cpufeature.c | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e04a8586067..041b4fd7a84c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -696,6 +696,12 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64mmfr0 */ +#define ID_AA64MMFR0_ECV_SHIFT 60 +#define ID_AA64MMFR0_FGT_SHIFT 56 +#define ID_AA64MMFR0_EXS_SHIFT 44 +#define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 +#define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 +#define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 @@ -831,6 +837,13 @@ #define ID_AA64MMFR0_TGRAN16_NI 0x0 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 +#define ID_AA64MMFR0_TGRAN4_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN4_2_SUPPORTED 0x2 +#define ID_AA64MMFR0_TGRAN64_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN64_2_SUPPORTED 0x2 +#define ID_AA64MMFR0_TGRAN16_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN16_2_SUPPORTED 0x2 + #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3d9c500555f3..3ab9f5b68d7b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -215,6 +215,10 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { + + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), /* * We already refuse to boot CPUs that don't support our configured * page size, so we can only detect mismatches for a page size other @@ -222,6 +226,9 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { * exist in the wild so, even though we don't like it, we'll have to go * along with it and treat them as non-strict. */ + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, ID_AA64MMFR0_TGRAN4_2_NI), + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, ID_AA64MMFR0_TGRAN64_2_NI), + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, ID_AA64MMFR0_TGRAN16_2_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, Anshuman Khandual <anshuman.khandual@arm.com>, linux-kernel@vger.kernel.org, maz@kernel.org, will@kernel.org Subject: [PATCH V2 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Date: Tue, 14 Apr 2020 15:18:26 +0530 [thread overview] Message-ID: <1586857710-17154-13-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1586857710-17154-1-git-send-email-anshuman.khandual@arm.com> Enable EVC, FGT, EXS, TGRAN4_2, TGRAN64_2 and TGRAN16_2 features bits in ID_AA64MMFR0 register as per ARM DDI 0487F.a specification. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Will Deacon <will@kernel.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/include/asm/sysreg.h | 13 +++++++++++++ arch/arm64/kernel/cpufeature.c | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e04a8586067..041b4fd7a84c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -696,6 +696,12 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64mmfr0 */ +#define ID_AA64MMFR0_ECV_SHIFT 60 +#define ID_AA64MMFR0_FGT_SHIFT 56 +#define ID_AA64MMFR0_EXS_SHIFT 44 +#define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 +#define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 +#define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 @@ -831,6 +837,13 @@ #define ID_AA64MMFR0_TGRAN16_NI 0x0 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 +#define ID_AA64MMFR0_TGRAN4_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN4_2_SUPPORTED 0x2 +#define ID_AA64MMFR0_TGRAN64_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN64_2_SUPPORTED 0x2 +#define ID_AA64MMFR0_TGRAN16_2_NI 0x1 +#define ID_AA64MMFR0_TGRAN16_2_SUPPORTED 0x2 + #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 3d9c500555f3..3ab9f5b68d7b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -215,6 +215,10 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { + + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), /* * We already refuse to boot CPUs that don't support our configured * page size, so we can only detect mismatches for a page size other @@ -222,6 +226,9 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { * exist in the wild so, even though we don't like it, we'll have to go * along with it and treat them as non-strict. */ + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, ID_AA64MMFR0_TGRAN4_2_NI), + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, ID_AA64MMFR0_TGRAN64_2_NI), + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, ID_AA64MMFR0_TGRAN16_2_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-14 9:50 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-14 9:48 [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual [this message] 2020-04-14 9:48 ` [PATCH V2 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-14 9:48 ` [PATCH V2 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual 2020-04-14 9:48 ` Anshuman Khandual 2020-04-29 9:37 ` [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual 2020-04-29 9:37 ` Anshuman Khandual 2020-04-29 9:37 ` Anshuman Khandual 2020-04-29 21:26 ` Will Deacon 2020-04-29 21:26 ` Will Deacon 2020-04-29 21:26 ` Will Deacon 2020-04-30 2:59 ` Anshuman Khandual 2020-04-30 2:59 ` Anshuman Khandual 2020-04-30 2:59 ` Anshuman Khandual 2020-04-30 16:47 ` Will Deacon 2020-04-30 16:47 ` Will Deacon 2020-04-30 16:47 ` Will Deacon
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