From: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
To: adrian.hunter@intel.com, ulf.hansson@linaro.org
Cc: bjorn.andersson@linaro.org, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Veerabhadrarao Badiganti <vbadigan@codeaurora.org>,
Andy Gross <agross@kernel.org>
Subject: [PATCH V2 3/3] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt
Date: Mon, 20 Apr 2020 11:50:25 +0530 [thread overview]
Message-ID: <1587363626-20413-4-git-send-email-vbadigan@codeaurora.org> (raw)
In-Reply-To: <1587363626-20413-1-git-send-email-vbadigan@codeaurora.org>
ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
ADMA length mismatch error interrupt. Enable it by default.
And update all bit shift defines with BIT macro.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 482045b..7d744f9 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -56,19 +56,19 @@
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)
-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
#define CORE_CLK_PWRSAVE BIT(1)
#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
#define CORE_HC_MCLK_SEL_MASK (3 << 8)
-#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
-#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
+#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
+#define CORE_IO_PAD_PWR_SWITCH BIT(16)
#define CORE_HC_SELECT_IN_EN BIT(18)
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)
-#define CORE_3_0V_SUPPORT (1 << 25)
-#define CORE_1_8V_SUPPORT (1 << 26)
+#define CORE_3_0V_SUPPORT BIT(25)
+#define CORE_1_8V_SUPPORT BIT(26)
#define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
#define CORE_CSR_CDC_CTLR_CFG0 0x130
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-04-20 6:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-20 6:20 [PATCH V2 0/3] Minor fixes to sdhci-msm Veerabhadrarao Badiganti
2020-04-20 6:20 ` [PATCH V2 1/3] mmc: sdhci-msm: Enable host capabilities pertains to R1b response Veerabhadrarao Badiganti
2020-04-20 6:20 ` [PATCH V2 2/3] mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk Veerabhadrarao Badiganti
2020-04-20 6:20 ` Veerabhadrarao Badiganti [this message]
2020-04-20 8:01 ` [PATCH V2 0/3] Minor fixes to sdhci-msm Ulf Hansson
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