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From: Shaokun Zhang <zhangshaokun@hisilicon.com>
To: <linux-arm-kernel@lists.infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Will Deacon <will@kernel.org>
Subject: [PATCH v3 3/3] arm64: perf: Correct the event index in sysfs
Date: Thu, 18 Jun 2020 21:35:44 +0800	[thread overview]
Message-ID: <1592487344-30555-3-git-send-email-zhangshaokun@hisilicon.com> (raw)
In-Reply-To: <1592487344-30555-1-git-send-email-zhangshaokun@hisilicon.com>

When PMU event ID is equal or greater than 0x4000, it will be reduced
by 0x4000 and it is not the raw number in the sysfs. Let's correct it
and obtain the raw event ID.

Before this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x001
After this patch:
cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed
event=0x4001

Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
 arch/arm64/kernel/perf_event.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 32c87cd48cbe..4bcdc94a780f 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -155,7 +155,7 @@ armv8pmu_events_sysfs_show(struct device *dev,
 
 	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 
-	return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
+	return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 }
 
 #define ARMV8_EVENT_ATTR(name, config)						\
@@ -263,10 +263,13 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj,
 	    test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 		return attr->mode;
 
-	pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
-	if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
-	    test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap))
-		return attr->mode;
+	if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
+		u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
+
+		if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && test_bit(id,
+			 cpu_pmu->pmceid_ext_bitmap))
+			return attr->mode;
+	}
 
 	return 0;
 }
-- 
2.7.4


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  parent reply	other threads:[~2020-06-18 13:37 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-18 13:35 [PATCH v3 1/3] arm64: perf: Add support caps in sysfs Shaokun Zhang
2020-06-18 13:35 ` [PATCH v3 2/3] arm64: perf: Expose some new events via sysfs Shaokun Zhang
2020-07-20 10:16   ` Will Deacon
2020-06-18 13:35 ` Shaokun Zhang [this message]
2020-07-20 10:20   ` [PATCH v3 3/3] arm64: perf: Correct the event index in sysfs Will Deacon
2020-07-07 13:33 ` [PATCH v3 1/3] arm64: perf: Add support caps " Shaokun Zhang
2020-07-20 10:15 ` Will Deacon
2020-07-20 10:50   ` Mark Rutland
2020-07-20 10:54     ` Will Deacon
2020-07-20 13:11       ` Shaokun Zhang
2020-07-21  8:05       ` Shaokun Zhang

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