From: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> To: mturquette@baylibre.com, m.tretter@pengutronix.de, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, jollys@xilinx.com, tejasp@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja <rajan.vaja@xilinx.com>, Tejas Patel <tejas.patel@xilinx.com>, Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> Subject: [PATCH v3 2/3] clk: zynqmp: Use firmware specific divider clock flags Date: Mon, 3 Aug 2020 23:44:16 -0700 [thread overview] Message-ID: <1596523457-40465-3-git-send-email-amit.sunil.dhamne@xilinx.com> (raw) In-Reply-To: <1596523457-40465-1-git-send-email-amit.sunil.dhamne@xilinx.com> From: Rajan Vaja <rajan.vaja@xilinx.com> Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> --- drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++ drivers/clk/zynqmp/divider.c | 24 +++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index 974d3da..9b2ff35e 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -32,6 +32,15 @@ /* do not gate, ever */ #define ZYNQMP_CLK_IS_CRITICAL BIT(11) +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + enum topology_type { TYPE_INVALID, TYPE_MUX, diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 775d54f..3b8fad0 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -283,6 +283,28 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) return ret_payload[1]; } +static inline unsigned long zynqmp_clk_map_divider_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ? + CLK_DIVIDER_ONE_BASED : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_POWER_OF_TWO : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ? + CLK_DIVIDER_ALLOW_ZERO : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_HIWORD_MASK : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ? + CLK_DIVIDER_ROUND_CLOSEST : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ? + CLK_DIVIDER_READ_ONLY : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ? + CLK_DIVIDER_MAX_AT_ZERO : 0; + return ccf_flag; +} + /** * zynqmp_clk_register_divider() - Register a divider clock * @name: Name of this clock @@ -320,7 +342,7 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, /* struct clk_divider assignments */ div->is_frac = !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); - div->flags = nodes->type_flag; + div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag); div->hw.init = &init; div->clk_id = clk_id; div->div_type = nodes->type; -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
WARNING: multiple messages have this Message-ID (diff)
From: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> To: mturquette@baylibre.com, m.tretter@pengutronix.de, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: Tejas Patel <tejas.patel@xilinx.com>, Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>, Rajan Vaja <rajan.vaja@xilinx.com>, tejasp@xilinx.com, linux-kernel@vger.kernel.org, jollys@xilinx.com, rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/3] clk: zynqmp: Use firmware specific divider clock flags Date: Mon, 3 Aug 2020 23:44:16 -0700 [thread overview] Message-ID: <1596523457-40465-3-git-send-email-amit.sunil.dhamne@xilinx.com> (raw) In-Reply-To: <1596523457-40465-1-git-send-email-amit.sunil.dhamne@xilinx.com> From: Rajan Vaja <rajan.vaja@xilinx.com> Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> --- drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++ drivers/clk/zynqmp/divider.c | 24 +++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h index 974d3da..9b2ff35e 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -32,6 +32,15 @@ /* do not gate, ever */ #define ZYNQMP_CLK_IS_CRITICAL BIT(11) +/* Type Flags for divider clock */ +#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) +#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) +#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) +#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) + enum topology_type { TYPE_INVALID, TYPE_MUX, diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 775d54f..3b8fad0 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -283,6 +283,28 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) return ret_payload[1]; } +static inline unsigned long zynqmp_clk_map_divider_ccf_flags( + const u32 zynqmp_type_flag) +{ + unsigned long ccf_flag = 0; + + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ? + CLK_DIVIDER_ONE_BASED : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_POWER_OF_TWO : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ? + CLK_DIVIDER_ALLOW_ZERO : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ? + CLK_DIVIDER_HIWORD_MASK : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ? + CLK_DIVIDER_ROUND_CLOSEST : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ? + CLK_DIVIDER_READ_ONLY : 0; + ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ? + CLK_DIVIDER_MAX_AT_ZERO : 0; + return ccf_flag; +} + /** * zynqmp_clk_register_divider() - Register a divider clock * @name: Name of this clock @@ -320,7 +342,7 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, /* struct clk_divider assignments */ div->is_frac = !!((nodes->flag & CLK_FRAC) | (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); - div->flags = nodes->type_flag; + div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag); div->hw.init = &init; div->clk_id = clk_id; div->div_type = nodes->type; -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-08-04 6:44 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-04 6:44 [PATCH v3 0/3] clk: zynqmp: Add firmware specific clock flags Amit Sunil Dhamne 2020-08-04 6:44 ` Amit Sunil Dhamne 2020-08-04 6:44 ` [PATCH v3 1/3] clk: zynqmp: Use firmware specific common " Amit Sunil Dhamne 2020-08-04 6:44 ` Amit Sunil Dhamne 2020-08-13 20:09 ` Stephen Boyd 2020-08-13 20:09 ` Stephen Boyd 2020-08-04 6:44 ` Amit Sunil Dhamne [this message] 2020-08-04 6:44 ` [PATCH v3 2/3] clk: zynqmp: Use firmware specific divider " Amit Sunil Dhamne 2020-08-04 6:44 ` [PATCH v3 3/3] clk: zynqmp: Use firmware specific mux " Amit Sunil Dhamne 2020-08-04 6:44 ` Amit Sunil Dhamne 2020-08-10 22:06 ` [PATCH v3 0/3] clk: zynqmp: Add firmware specific " Amit Sunil Dhamne 2020-08-10 22:06 ` Amit Sunil Dhamne
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