From: Cathy Zhang <cathy.zhang@intel.com>
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org
Cc: pbonzini@redhat.com, sean.j.christopherson@intel.com,
gregkh@linuxfoundation.org, tglx@linutronix.de,
tony.luck@intel.com, dave.hansen@intel.com,
kyung.min.park@intel.com, ricardo.neri-calderon@linux.intel.com,
vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com,
joro@8bytes.org, mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
jpoimboe@redhat.com, ak@linux.intel.com,
ravi.v.shankar@intel.com, Cathy Zhang <cathy.zhang@intel.com>
Subject: [PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
Date: Sun, 9 Aug 2020 15:47:21 +0800 [thread overview]
Message-ID: <1596959242-2372-2-git-send-email-cathy.zhang@intel.com> (raw)
In-Reply-To: <1596959242-2372-1-git-send-email-cathy.zhang@intel.com>
From: Kyung Min Park <kyung.min.park@intel.com>
Intel TSX suspend load tracking instructions aim to give a way to
choose which memory accesses do not need to be tracked in the TSX
read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
for enumeration.
A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.
The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
This instruction is currently documented in the the latest "extensions"
manual (ISE). It will appear in the "main" manual (SDM) in the future.
Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
Changes since v2:
* Shorten documentation names for readability. Links to documentation
can be found in the cover letter. (Dave Hansen)
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 2901d5d..83fc9d3 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -368,6 +368,7 @@
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
--
1.8.3.1
next prev parent reply other threads:[~2020-08-09 7:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-09 7:47 [PATCH v3 0/2] Expose new features for Intel processor Cathy Zhang
2020-08-09 7:47 ` Cathy Zhang [this message]
2020-08-09 7:47 ` [PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid Cathy Zhang
2020-08-09 17:14 ` Paolo Bonzini
2020-08-10 23:50 ` Zhang, Cathy
2020-08-10 23:59 ` Luck, Tony
2020-08-11 0:18 ` Zhang, Cathy
2020-08-11 8:32 ` Paolo Bonzini
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