From: Swapnil Jakhade <sjakhade@cadence.com> To: <airlied@linux.ie>, <daniel@ffwll.ch>, <Laurent.pinchart@ideasonboard.com>, <robh+dt@kernel.org>, <a.hajda@samsung.com>, <narmstrong@baylibre.com>, <jonas@kwiboo.se>, <jernej.skrabec@siol.net>, <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>, <nsekhar@ti.com>, <praneeth@ti.com>, <nikhil.nd@ti.com>, <vkoul@kernel.org> Subject: [PATCH v11 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings Date: Fri, 18 Sep 2020 14:09:21 +0200 [thread overview] Message-ID: <1600430963-23753-2-git-send-email-sjakhade@cadence.com> (raw) In-Reply-To: <1600430963-23753-1-git-send-email-sjakhade@cadence.com> From: Yuti Amonkar <yamonkar@cadence.com> Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in yaml format. Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- .../display/bridge/cdns,mhdp8546.yaml | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml new file mode 100644 index 000000000000..74d675fc6e7b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence MHDP8546 bridge + +maintainers: + - Swapnil Jakhade <sjakhade@cadence.com> + - Yuti Amonkar <yamonkar@cadence.com> + +properties: + compatible: + enum: + - cdns,mhdp8546 + - ti,j721e-mhdp8546 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they are instead + included in the associated PHY. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: mhdptx + - const: j721e-intg + + clocks: + maxItems: 1 + description: + DP bridge clock, used by the IP to know how to translate a number of + clock cycles into a time (which is used to comply with DP standard timings + and delays). + + phys: + maxItems: 1 + description: + phandle to the DisplayPort PHY. + + phy-names: + items: + - const: dpphy + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + type: object + description: + Ports as described in Documentation/devicetree/bindings/graph.txt. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: + First input port representing the DP bridge input. + + port@1: + type: object + description: + Second input port representing the DP bridge input. + + port@2: + type: object + description: + Third input port representing the DP bridge input. + + port@3: + type: object + description: + Fourth input port representing the DP bridge input. + + port@4: + type: object + description: + Output port representing the DP bridge output. + + required: + - port@0 + - port@4 + - '#address-cells' + - '#size-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: ti,j721e-mhdp8546 + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + +required: + - compatible + - clocks + - reg + - reg-names + - phys + - phy-names + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + mhdp: dp-bridge@f0fb000000 { + compatible = "cdns,mhdp8546"; + reg = <0xf0 0xfb000000 0x0 0x1000000>; + reg-names = "mhdptx"; + clocks = <&mhdp_clock>; + phys = <&dp_phy>; + phy-names = "dpphy"; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_bridge_input: endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + + port@4 { + reg = <4>; + dp_bridge_output: endpoint { + remote-endpoint = <&xxx_dp_connector_input>; + }; + }; + }; + }; + }; +... -- 2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Swapnil Jakhade <sjakhade@cadence.com> To: <airlied@linux.ie>, <daniel@ffwll.ch>, <Laurent.pinchart@ideasonboard.com>, <robh+dt@kernel.org>, <a.hajda@samsung.com>, <narmstrong@baylibre.com>, <jonas@kwiboo.se>, <jernej.skrabec@siol.net>, <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Cc: mparab@cadence.com, yamonkar@cadence.com, praneeth@ti.com, nsekhar@ti.com, jsarha@ti.com, vkoul@kernel.org, tomi.valkeinen@ti.com, sjakhade@cadence.com, nikhil.nd@ti.com Subject: [PATCH v11 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings Date: Fri, 18 Sep 2020 14:09:21 +0200 [thread overview] Message-ID: <1600430963-23753-2-git-send-email-sjakhade@cadence.com> (raw) In-Reply-To: <1600430963-23753-1-git-send-email-sjakhade@cadence.com> From: Yuti Amonkar <yamonkar@cadence.com> Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in yaml format. Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- .../display/bridge/cdns,mhdp8546.yaml | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml new file mode 100644 index 000000000000..74d675fc6e7b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence MHDP8546 bridge + +maintainers: + - Swapnil Jakhade <sjakhade@cadence.com> + - Yuti Amonkar <yamonkar@cadence.com> + +properties: + compatible: + enum: + - cdns,mhdp8546 + - ti,j721e-mhdp8546 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they are instead + included in the associated PHY. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: mhdptx + - const: j721e-intg + + clocks: + maxItems: 1 + description: + DP bridge clock, used by the IP to know how to translate a number of + clock cycles into a time (which is used to comply with DP standard timings + and delays). + + phys: + maxItems: 1 + description: + phandle to the DisplayPort PHY. + + phy-names: + items: + - const: dpphy + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + type: object + description: + Ports as described in Documentation/devicetree/bindings/graph.txt. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: + First input port representing the DP bridge input. + + port@1: + type: object + description: + Second input port representing the DP bridge input. + + port@2: + type: object + description: + Third input port representing the DP bridge input. + + port@3: + type: object + description: + Fourth input port representing the DP bridge input. + + port@4: + type: object + description: + Output port representing the DP bridge output. + + required: + - port@0 + - port@4 + - '#address-cells' + - '#size-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: ti,j721e-mhdp8546 + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + +required: + - compatible + - clocks + - reg + - reg-names + - phys + - phy-names + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + mhdp: dp-bridge@f0fb000000 { + compatible = "cdns,mhdp8546"; + reg = <0xf0 0xfb000000 0x0 0x1000000>; + reg-names = "mhdptx"; + clocks = <&mhdp_clock>; + phys = <&dp_phy>; + phy-names = "dpphy"; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_bridge_input: endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + + port@4 { + reg = <4>; + dp_bridge_output: endpoint { + remote-endpoint = <&xxx_dp_connector_input>; + }; + }; + }; + }; + }; +... -- 2.26.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-09-18 12:10 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-18 12:09 [PATCH v11 0/3] drm: Add support for Cadence MHDP8546 DPI/DP bridge and J721E wrapper Swapnil Jakhade 2020-09-18 12:09 ` Swapnil Jakhade 2020-09-18 12:09 ` Swapnil Jakhade [this message] 2020-09-18 12:09 ` [PATCH v11 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings Swapnil Jakhade 2020-09-18 12:09 ` [PATCH v11 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge Swapnil Jakhade 2020-09-18 12:09 ` Swapnil Jakhade 2020-10-01 0:20 ` kernel test robot 2020-09-18 12:09 ` [PATCH v11 3/3] drm: bridge: cdns-mhdp8546: Add TI J721E wrapper Swapnil Jakhade 2020-09-18 12:09 ` Swapnil Jakhade
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