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From: John Garry <john.garry@huawei.com>
To: <acme@kernel.org>, <will@kernel.org>, <mark.rutland@arm.com>,
	<jolsa@redhat.com>, <irogers@google.com>, <leo.yan@linaro.org>,
	<peterz@infradead.org>, <mingo@redhat.com>,
	<alexander.shishkin@linux.intel.com>, <namhyung@kernel.org>,
	<mathieu.poirier@linaro.org>
Cc: <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <qiangqing.zhang@nxp.com>,
	<zhangshaokun@hisilicon.com>, <linux-imx@nxp.com>,
	<kjain@linux.ibm.com>, John Garry <john.garry@huawei.com>
Subject: [PATCH RFC v5 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events
Date: Fri, 6 Nov 2020 20:35:46 +0800	[thread overview]
Message-ID: <1604666153-4187-7-git-send-email-john.garry@huawei.com> (raw)
In-Reply-To: <1604666153-4187-1-git-send-email-john.garry@huawei.com>

Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.

This contains a mix of architected and IMP def events, but for now only a
single event is added.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../hisilicon/hip09/sys/smmu-v3-pmcg.json     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
new file mode 100644
index 000000000000..9f4c35a0b499
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
@@ -0,0 +1,42 @@
+[
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CYCLES"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "EventCode": "0x8a",
+	    "EventName": "smmuv3_pmcg.L1_TLB",
+	    "BriefDescription": "SMMUv3 PMCG command received by L1 TLB",
+	    "PublicDescription": "SMMUv3 PMCG command received by L1 TLB",
+	    "Unit": "smmuv3_pmcg",
+	    "Compat": "0x00030736"
+   },
+]
-- 
2.26.2


WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry@huawei.com>
To: <acme@kernel.org>, <will@kernel.org>, <mark.rutland@arm.com>,
	<jolsa@redhat.com>, <irogers@google.com>, <leo.yan@linaro.org>,
	<peterz@infradead.org>, <mingo@redhat.com>,
	<alexander.shishkin@linux.intel.com>, <namhyung@kernel.org>,
	<mathieu.poirier@linaro.org>
Cc: linux-kernel@vger.kernel.org, John Garry <john.garry@huawei.com>,
	qiangqing.zhang@nxp.com, linuxarm@huawei.com,
	zhangshaokun@hisilicon.com, linux-imx@nxp.com,
	kjain@linux.ibm.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC v5 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events
Date: Fri, 6 Nov 2020 20:35:46 +0800	[thread overview]
Message-ID: <1604666153-4187-7-git-send-email-john.garry@huawei.com> (raw)
In-Reply-To: <1604666153-4187-1-git-send-email-john.garry@huawei.com>

Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.

This contains a mix of architected and IMP def events, but for now only a
single event is added.

Signed-off-by: John Garry <john.garry@huawei.com>
---
 .../hisilicon/hip09/sys/smmu-v3-pmcg.json     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
new file mode 100644
index 000000000000..9f4c35a0b499
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
@@ -0,0 +1,42 @@
+[
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CYCLES"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "EventCode": "0x8a",
+	    "EventName": "smmuv3_pmcg.L1_TLB",
+	    "BriefDescription": "SMMUv3 PMCG command received by L1 TLB",
+	    "PublicDescription": "SMMUv3 PMCG command received by L1 TLB",
+	    "Unit": "smmuv3_pmcg",
+	    "Compat": "0x00030736"
+   },
+]
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-11-06 12:40 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-06 12:35 [PATCH RFC v5 00/13] perf pmu-events: Support event aliasing for system PMUs John Garry
2020-11-06 12:35 ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 01/13] perf jevents: Add support for an extra directory level John Garry
2020-11-06 12:35   ` John Garry
2020-11-13  8:48   ` kajoljain
2020-11-13  8:48     ` kajoljain
2020-11-13  9:24     ` John Garry
2020-11-13  9:24       ` John Garry
2020-11-18  4:38       ` kajoljain
2020-11-18  4:38         ` kajoljain
2020-11-06 12:35 ` [PATCH RFC v5 02/13] perf jevents: Add support for system events tables John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 03/13] perf pmu: Add pmu_id() John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 04/13] perf pmu: Add pmu_add_sys_aliases() John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 05/13] perf vendor events arm64: Add Architected events smmuv3-pmcg.json John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` John Garry [this message]
2020-11-06 12:35   ` [PATCH RFC v5 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events John Garry
2020-11-06 12:35 ` [PATCH RFC v5 07/13] perf vendor events arm64: Add hip09 uncore events John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 08/13] perf evlist: Change perf_evlist__splice_list_tail() ordering John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 09/13] perf metricgroup: Fix metrics using aliases covering multiple PMUs John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 10/13] perf metricgroup: Split up metricgroup__print() John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 11/13] perf metricgroup: Support printing metric groups for system PMUs John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 12/13] perf metricgroup: Support adding metrics " John Garry
2020-11-06 12:35   ` John Garry
2020-11-06 12:35 ` [PATCH RFC v5 13/13] perf vendor events: Add JSON metrics for imx8mm DDR Perf John Garry
2020-11-06 12:35   ` John Garry
2020-11-29  6:25 ` [PATCH RFC v5 00/13] perf pmu-events: Support event aliasing for system PMUs kajoljain
2020-11-29  6:25   ` kajoljain

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