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From: Stefan Wahren <stefan.wahren@i2se.com>
To: Eric Anholt <eric@anholt.net>, Maxime Ripard <mripard@kernel.org>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Phil Elwell <phil@raspberrypi.org>,
	Stefan Wahren <stefan.wahren@i2se.com>
Subject: [PATCH V2 3/4] drm/v3d: Don't clear MMU control bits on exception
Date: Wed, 23 Dec 2020 21:35:13 +0100	[thread overview]
Message-ID: <1608755714-18233-4-git-send-email-stefan.wahren@i2se.com> (raw)
In-Reply-To: <1608755714-18233-1-git-send-email-stefan.wahren@i2se.com>

From: Phil Elwell <phil@raspberrypi.org>

MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that register,
including MMU_ENABLE, so a safer approach is to simply write back the
value just read unaltered.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
 drivers/gpu/drm/v3d/v3d_irq.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c
index 0be2eb7..e714d53 100644
--- a/drivers/gpu/drm/v3d/v3d_irq.c
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
 		};
 		const char *client = "?";
 
-		V3D_WRITE(V3D_MMU_CTL,
-			  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
-						   V3D_MMU_CTL_PT_INVALID |
-						   V3D_MMU_CTL_WRITE_VIOLATION));
+		V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
 
 		if (v3d->ver >= 41) {
 			axi_id = axi_id >> 5;
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Stefan Wahren <stefan.wahren@i2se.com>
To: Eric Anholt <eric@anholt.net>, Maxime Ripard <mripard@kernel.org>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>,
	devicetree@vger.kernel.org, Phil Elwell <phil@raspberrypi.org>,
	linux-arm-kernel@lists.infradead.org,
	dri-devel@lists.freedesktop.org
Subject: [PATCH V2 3/4] drm/v3d: Don't clear MMU control bits on exception
Date: Wed, 23 Dec 2020 21:35:13 +0100	[thread overview]
Message-ID: <1608755714-18233-4-git-send-email-stefan.wahren@i2se.com> (raw)
In-Reply-To: <1608755714-18233-1-git-send-email-stefan.wahren@i2se.com>

From: Phil Elwell <phil@raspberrypi.org>

MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that register,
including MMU_ENABLE, so a safer approach is to simply write back the
value just read unaltered.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
 drivers/gpu/drm/v3d/v3d_irq.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c
index 0be2eb7..e714d53 100644
--- a/drivers/gpu/drm/v3d/v3d_irq.c
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
 		};
 		const char *client = "?";
 
-		V3D_WRITE(V3D_MMU_CTL,
-			  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
-						   V3D_MMU_CTL_PT_INVALID |
-						   V3D_MMU_CTL_WRITE_VIOLATION));
+		V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
 
 		if (v3d->ver >= 41) {
 			axi_id = axi_id >> 5;
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Stefan Wahren <stefan.wahren@i2se.com>
To: Eric Anholt <eric@anholt.net>, Maxime Ripard <mripard@kernel.org>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>,
	devicetree@vger.kernel.org, Phil Elwell <phil@raspberrypi.org>,
	linux-arm-kernel@lists.infradead.org,
	dri-devel@lists.freedesktop.org
Subject: [PATCH V2 3/4] drm/v3d: Don't clear MMU control bits on exception
Date: Wed, 23 Dec 2020 21:35:13 +0100	[thread overview]
Message-ID: <1608755714-18233-4-git-send-email-stefan.wahren@i2se.com> (raw)
In-Reply-To: <1608755714-18233-1-git-send-email-stefan.wahren@i2se.com>

From: Phil Elwell <phil@raspberrypi.org>

MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that register,
including MMU_ENABLE, so a safer approach is to simply write back the
value just read unaltered.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
 drivers/gpu/drm/v3d/v3d_irq.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/v3d/v3d_irq.c b/drivers/gpu/drm/v3d/v3d_irq.c
index 0be2eb7..e714d53 100644
--- a/drivers/gpu/drm/v3d/v3d_irq.c
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
 		};
 		const char *client = "?";
 
-		V3D_WRITE(V3D_MMU_CTL,
-			  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
-						   V3D_MMU_CTL_PT_INVALID |
-						   V3D_MMU_CTL_WRITE_VIOLATION));
+		V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
 
 		if (v3d->ver >= 41) {
 			axi_id = axi_id >> 5;
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  parent reply	other threads:[~2020-12-23 20:38 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-23 20:35 [PATCH V2 0/4] drm/v3d: Minor improvements Stefan Wahren
2020-12-23 20:35 ` Stefan Wahren
2020-12-23 20:35 ` Stefan Wahren
2020-12-23 20:35 ` [PATCH V2 1/4] drm/v3d: Use platform_get_irq_optional() to get optional IRQs Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2021-01-06 15:09   ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2020-12-23 20:35 ` [PATCH V2 2/4] drm/v3d: Set dma_mask as well as coherent_dma_mask Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2020-12-24 13:58   ` Nicolas Saenz Julienne
2020-12-24 13:58     ` Nicolas Saenz Julienne
2020-12-24 13:58     ` Nicolas Saenz Julienne
2021-01-06 15:09   ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2020-12-23 20:35 ` Stefan Wahren [this message]
2020-12-23 20:35   ` [PATCH V2 3/4] drm/v3d: Don't clear MMU control bits on exception Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2020-12-24 13:59   ` Nicolas Saenz Julienne
2020-12-24 13:59     ` Nicolas Saenz Julienne
2020-12-24 13:59     ` Nicolas Saenz Julienne
2021-01-06 15:09   ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2021-01-06 15:09     ` Maxime Ripard
2020-12-23 20:35 ` [PATCH V2 4/4] dt-bindings: gpu: Convert v3d to json-schema Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2020-12-23 20:35   ` Stefan Wahren
2021-01-06 15:12   ` Maxime Ripard
2021-01-06 15:12     ` Maxime Ripard
2021-01-06 15:12     ` Maxime Ripard

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