From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, mike.leach@linaro.org, lcherian@marvell.com, linux-kernel@vger.kernel.org, Anshuman Khandual <anshuman.khandual@arm.com> Subject: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Date: Wed, 27 Jan 2021 14:25:27 +0530 [thread overview] Message-ID: <1611737738-1493-4-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1611737738-1493-1-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose <suzuki.poulose@arm.com> ETE may not implement the OS lock and instead could rely on the PE OS Lock for the trace unit access. This is indicated by the TRCOLSR.OSM == 0b100. Add support for handling the PE OS lock Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++ 2 files changed, 56 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 473ab74..9edf8be 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) } } -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) { - /* Writing 0 to TRCOSLAR unlocks the trace registers */ - etm4x_relaxed_write32(csa, 0x0, TRCOSLAR); - drvdata->os_unlock = true; + u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); + + drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); +} + +static void etm_write_os_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa, u32 val) +{ + val = !!val; + + switch (drvdata->os_lock_model) { + case ETM_OSLOCK_PRESENT: + etm4x_relaxed_write32(csa, val, TRCOSLAR); + break; + case ETM_OSLOCK_PE: + write_sysreg_s(val, SYS_OSLAR_EL1); + break; + default: + pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", + smp_processor_id(), drvdata->os_lock_model); + fallthrough; + case ETM_OSLOCK_NI: + return; + } isb(); } +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + WARN_ON(drvdata->cpu != smp_processor_id()); + + /* Writing 0 to OS Lock unlocks the trace unit registers */ + etm_write_os_lock(drvdata, csa, 0x0); + drvdata->os_unlock = true; +} + static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { if (!WARN_ON(!drvdata->csdev)) etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); - } static void etm4_os_lock(struct etmv4_drvdata *drvdata) { if (WARN_ON(!drvdata->csdev)) return; - - /* Writing 0x1 to TRCOSLAR locks the trace registers */ - etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR); + /* Writing 0x1 to OS Lock locks the trace registers */ + etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1); drvdata->os_unlock = false; - isb(); } static void etm4_cs_lock(struct etmv4_drvdata *drvdata, @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info) if (!etm4_init_csdev_access(drvdata, csa)) return; + /* Detect the support for OS Lock before we actuall use it */ + etm_detect_os_lock(drvdata, csa); + /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 0af6057..0e86eba 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -506,6 +506,20 @@ ETM_MODE_EXCL_USER) /* + * TRCOSLSR.OSLM advertises the OS Lock model. + * OSLM[2:0] = TRCOSLSR[4:3,0] + * + * 0b000 - Trace OS Lock is not implemented. + * 0b010 - Trace OS Lock is implemented. + * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock. + */ +#define ETM_OSLOCK_NI 0b000 +#define ETM_OSLOCK_PRESENT 0b010 +#define ETM_OSLOCK_PE 0b100 + +#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1)) + +/* * TRCDEVARCH Bit field definitions * Bits[31:21] - ARCHITECT = Always Arm Ltd. * * Bits[31:28] = 0x4 @@ -897,6 +911,7 @@ struct etmv4_drvdata { u8 s_ex_level; u8 ns_ex_level; u8 q_support; + u8 os_lock_model; bool sticky_enable; bool boot_enable; bool os_unlock; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org Cc: mathieu.poirier@linaro.org, Anshuman Khandual <anshuman.khandual@arm.com>, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org, lcherian@marvell.com, mike.leach@linaro.org Subject: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Date: Wed, 27 Jan 2021 14:25:27 +0530 [thread overview] Message-ID: <1611737738-1493-4-git-send-email-anshuman.khandual@arm.com> (raw) In-Reply-To: <1611737738-1493-1-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose <suzuki.poulose@arm.com> ETE may not implement the OS lock and instead could rely on the PE OS Lock for the trace unit access. This is indicated by the TRCOLSR.OSM == 0b100. Add support for handling the PE OS lock Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++ 2 files changed, 56 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 473ab74..9edf8be 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) } } -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) { - /* Writing 0 to TRCOSLAR unlocks the trace registers */ - etm4x_relaxed_write32(csa, 0x0, TRCOSLAR); - drvdata->os_unlock = true; + u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); + + drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); +} + +static void etm_write_os_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa, u32 val) +{ + val = !!val; + + switch (drvdata->os_lock_model) { + case ETM_OSLOCK_PRESENT: + etm4x_relaxed_write32(csa, val, TRCOSLAR); + break; + case ETM_OSLOCK_PE: + write_sysreg_s(val, SYS_OSLAR_EL1); + break; + default: + pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", + smp_processor_id(), drvdata->os_lock_model); + fallthrough; + case ETM_OSLOCK_NI: + return; + } isb(); } +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + WARN_ON(drvdata->cpu != smp_processor_id()); + + /* Writing 0 to OS Lock unlocks the trace unit registers */ + etm_write_os_lock(drvdata, csa, 0x0); + drvdata->os_unlock = true; +} + static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { if (!WARN_ON(!drvdata->csdev)) etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); - } static void etm4_os_lock(struct etmv4_drvdata *drvdata) { if (WARN_ON(!drvdata->csdev)) return; - - /* Writing 0x1 to TRCOSLAR locks the trace registers */ - etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR); + /* Writing 0x1 to OS Lock locks the trace registers */ + etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1); drvdata->os_unlock = false; - isb(); } static void etm4_cs_lock(struct etmv4_drvdata *drvdata, @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info) if (!etm4_init_csdev_access(drvdata, csa)) return; + /* Detect the support for OS Lock before we actuall use it */ + etm_detect_os_lock(drvdata, csa); + /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 0af6057..0e86eba 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -506,6 +506,20 @@ ETM_MODE_EXCL_USER) /* + * TRCOSLSR.OSLM advertises the OS Lock model. + * OSLM[2:0] = TRCOSLSR[4:3,0] + * + * 0b000 - Trace OS Lock is not implemented. + * 0b010 - Trace OS Lock is implemented. + * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock. + */ +#define ETM_OSLOCK_NI 0b000 +#define ETM_OSLOCK_PRESENT 0b010 +#define ETM_OSLOCK_PE 0b100 + +#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1)) + +/* * TRCDEVARCH Bit field definitions * Bits[31:21] - ARCHITECT = Always Arm Ltd. * * Bits[31:28] = 0x4 @@ -897,6 +911,7 @@ struct etmv4_drvdata { u8 s_ex_level; u8 ns_ex_level; u8 q_support; + u8 os_lock_model; bool sticky_enable; bool boot_enable; bool os_unlock; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-27 8:59 UTC|newest] Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-01 23:17 ` Mathieu Poirier 2021-02-01 23:17 ` Mathieu Poirier 2021-02-02 9:42 ` Suzuki K Poulose 2021-02-02 9:42 ` Suzuki K Poulose 2021-02-02 16:33 ` Mike Leach 2021-02-02 16:33 ` Mike Leach 2021-02-02 22:41 ` Suzuki K Poulose 2021-02-02 22:41 ` Suzuki K Poulose 2021-02-04 12:27 ` Mike Leach 2021-02-04 12:27 ` Mike Leach 2021-02-02 16:37 ` Mathieu Poirier 2021-02-02 16:37 ` Mathieu Poirier 2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-01 23:44 ` Mathieu Poirier 2021-02-01 23:44 ` Mathieu Poirier 2021-02-02 11:10 ` Mike Leach 2021-02-02 11:10 ` Mike Leach 2021-02-02 14:36 ` Suzuki K Poulose 2021-02-02 14:36 ` Suzuki K Poulose 2021-01-27 8:55 ` Anshuman Khandual [this message] 2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual 2021-02-02 17:40 ` Mathieu Poirier 2021-02-02 17:40 ` Mathieu Poirier 2021-02-02 18:03 ` Mathieu Poirier 2021-02-02 18:03 ` Mathieu Poirier 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-02 17:52 ` Mathieu Poirier 2021-02-02 17:52 ` Mathieu Poirier 2021-02-03 15:51 ` Suzuki K Poulose 2021-02-03 15:51 ` Suzuki K Poulose 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-02 18:56 ` Mathieu Poirier 2021-02-02 18:56 ` Mathieu Poirier 2021-02-02 22:50 ` Suzuki K Poulose 2021-02-02 22:50 ` Suzuki K Poulose 2021-02-15 13:21 ` Mike Leach 2021-02-15 13:21 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-09 19:00 ` Rob Herring 2021-02-09 19:00 ` Rob Herring 2021-02-10 12:33 ` Suzuki K Poulose 2021-02-10 12:33 ` Suzuki K Poulose 2021-02-18 18:33 ` Rob Herring 2021-02-18 18:33 ` Rob Herring 2021-02-18 22:51 ` Suzuki K Poulose 2021-02-18 22:51 ` Suzuki K Poulose 2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-03 19:05 ` Mathieu Poirier 2021-02-03 19:05 ` Mathieu Poirier 2021-02-03 23:36 ` Suzuki K Poulose 2021-02-03 23:36 ` Suzuki K Poulose 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:27 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-28 9:16 ` Suzuki K Poulose 2021-01-28 9:16 ` Suzuki K Poulose 2021-02-04 18:34 ` Mathieu Poirier 2021-02-04 18:34 ` Mathieu Poirier 2021-02-16 10:40 ` Anshuman Khandual 2021-02-16 10:40 ` Anshuman Khandual 2021-02-16 20:44 ` Mathieu Poirier 2021-02-16 20:44 ` Mathieu Poirier 2021-02-16 10:21 ` Anshuman Khandual 2021-02-16 10:21 ` Anshuman Khandual 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:56 ` Mathieu Poirier 2021-02-15 16:56 ` Mathieu Poirier 2021-02-15 17:58 ` Mike Leach 2021-02-15 17:58 ` Mike Leach 2021-02-16 20:30 ` Mathieu Poirier 2021-02-16 20:30 ` Mathieu Poirier 2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-28 9:31 ` Suzuki K Poulose 2021-01-28 9:31 ` Suzuki K Poulose 2021-01-28 17:18 ` Catalin Marinas 2021-01-28 17:18 ` Catalin Marinas 2021-02-15 18:06 ` Mike Leach 2021-02-15 18:06 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 9:58 ` Marc Zyngier 2021-01-27 9:58 ` Marc Zyngier 2021-01-28 9:34 ` Suzuki K Poulose 2021-01-28 9:34 ` Suzuki K Poulose 2021-01-28 9:46 ` Marc Zyngier 2021-01-28 9:46 ` Marc Zyngier 2021-01-28 9:48 ` Suzuki K Poulose 2021-01-28 9:48 ` Suzuki K Poulose 2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-29 10:23 ` Suzuki K Poulose 2021-02-02 5:55 ` Anshuman Khandual 2021-02-02 5:55 ` Anshuman Khandual 2021-02-05 17:53 ` Mathieu Poirier 2021-02-05 17:53 ` Mathieu Poirier 2021-02-08 4:20 ` Anshuman Khandual 2021-02-08 4:20 ` Anshuman Khandual 2021-02-09 17:39 ` Mathieu Poirier 2021-02-09 17:39 ` Mathieu Poirier 2021-02-10 4:12 ` Anshuman Khandual 2021-02-10 4:12 ` Anshuman Khandual 2021-02-10 16:54 ` Mathieu Poirier 2021-02-10 16:54 ` Mathieu Poirier 2021-02-10 19:00 ` Mathieu Poirier 2021-02-10 19:00 ` Mathieu Poirier 2021-02-12 5:43 ` Anshuman Khandual 2021-02-12 5:43 ` Anshuman Khandual 2021-02-12 17:02 ` Mathieu Poirier 2021-02-12 17:02 ` Mathieu Poirier 2021-02-11 19:00 ` Mathieu Poirier 2021-02-11 19:00 ` Mathieu Poirier 2021-02-12 3:31 ` Anshuman Khandual 2021-02-12 3:31 ` Anshuman Khandual 2021-02-12 16:57 ` Mathieu Poirier 2021-02-12 16:57 ` Mathieu Poirier 2021-02-15 9:26 ` Anshuman Khandual 2021-02-15 9:26 ` Anshuman Khandual 2021-02-12 20:26 ` Mathieu Poirier 2021-02-12 20:26 ` Mathieu Poirier 2021-02-15 9:46 ` Anshuman Khandual 2021-02-15 9:46 ` Anshuman Khandual 2021-02-16 9:00 ` Mike Leach 2021-02-16 9:00 ` Mike Leach 2021-02-16 9:44 ` Anshuman Khandual 2021-02-16 9:44 ` Anshuman Khandual 2021-02-16 12:12 ` Mike Leach 2021-02-16 12:12 ` Mike Leach 2021-02-18 7:50 ` Suzuki K Poulose 2021-02-18 7:50 ` Suzuki K Poulose 2021-02-18 14:30 ` Mike Leach 2021-02-18 14:30 ` Mike Leach 2021-02-18 15:14 ` Suzuki K Poulose 2021-02-18 15:14 ` Suzuki K Poulose 2021-02-22 10:42 ` Mike Leach 2021-02-22 10:42 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-09 19:04 ` Rob Herring 2021-02-09 19:04 ` Rob Herring 2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 12:51 ` Peter Zijlstra 2021-01-27 12:51 ` Peter Zijlstra 2021-02-16 10:59 ` Mike Leach 2021-02-16 10:59 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 12:54 ` Peter Zijlstra 2021-01-27 12:54 ` Peter Zijlstra 2021-01-27 13:00 ` Al Grant 2021-01-27 13:00 ` Al Grant 2021-02-18 3:05 ` Anshuman Khandual 2021-02-18 3:05 ` Anshuman Khandual 2021-01-27 14:12 ` Suzuki K Poulose 2021-01-27 14:12 ` Suzuki K Poulose 2021-02-16 11:01 ` Mike Leach 2021-02-16 11:01 ` Mike Leach 2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier 2021-01-27 18:50 ` Mathieu Poirier 2021-02-01 18:44 ` Mathieu Poirier 2021-02-01 18:44 ` Mathieu Poirier 2021-02-18 4:23 ` Anshuman Khandual 2021-02-18 4:23 ` Anshuman Khandual
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