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From: peng.fan@oss.nxp.com
To: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
	s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	ulf.hansson@linaro.org, adrian.hunter@intel.com,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
	Peng Fan <peng.fan@nxp.com>
Subject: [PATCH V3 3/5] arm64: dts: imx8qxp: correct usdhc clock-names sequence
Date: Thu, 25 Feb 2021 11:10:02 +0800	[thread overview]
Message-ID: <1614222604-27066-4-git-send-email-peng.fan@oss.nxp.com> (raw)
In-Reply-To: <1614222604-27066-1-git-send-email-peng.fan@oss.nxp.com>

From: Peng Fan <peng.fan@nxp.com>

Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..1d522de7b017 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -366,9 +366,9 @@ usdhc1: mmc@5b010000 {
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b010000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_0>;
 			status = "disabled";
 		};
@@ -378,9 +378,9 @@ usdhc2: mmc@5b020000 {
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b020000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_1>;
 			fsl,tuning-start-tap = <20>;
 			fsl,tuning-step= <2>;
@@ -392,9 +392,9 @@ usdhc3: mmc@5b030000 {
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b030000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_2>;
 			status = "disabled";
 		};
-- 
2.30.0


WARNING: multiple messages have this Message-ID (diff)
From: peng.fan@oss.nxp.com
To: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
	s.hauer@pengutronix.de
Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org,
	linux-mmc@vger.kernel.org, adrian.hunter@intel.com,
	linux-kernel@vger.kernel.org, linux-imx@nxp.com,
	kernel@pengutronix.de, Peng Fan <peng.fan@nxp.com>,
	festevam@gmail.com, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH V3 3/5] arm64: dts: imx8qxp: correct usdhc clock-names sequence
Date: Thu, 25 Feb 2021 11:10:02 +0800	[thread overview]
Message-ID: <1614222604-27066-4-git-send-email-peng.fan@oss.nxp.com> (raw)
In-Reply-To: <1614222604-27066-1-git-send-email-peng.fan@oss.nxp.com>

From: Peng Fan <peng.fan@nxp.com>

Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..1d522de7b017 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -366,9 +366,9 @@ usdhc1: mmc@5b010000 {
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b010000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_0>;
 			status = "disabled";
 		};
@@ -378,9 +378,9 @@ usdhc2: mmc@5b020000 {
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b020000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_1>;
 			fsl,tuning-start-tap = <20>;
 			fsl,tuning-step= <2>;
@@ -392,9 +392,9 @@ usdhc3: mmc@5b030000 {
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b030000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_2>;
 			status = "disabled";
 		};
-- 
2.30.0


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-02-25  3:25 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25  3:09 [PATCH V3 0/5] imx esdhc dt/driver update peng.fan
2021-02-25  3:09 ` peng.fan
2021-02-25  3:10 ` [PATCH V3 1/5] dt-bindings: mmc: fsl-imx-esdhc: add pinctrl bindings peng.fan
2021-02-25  3:10   ` peng.fan
2021-02-25  3:10 ` [PATCH V3 2/5] dt-bindings: clock: imx8qxp-lpcg: correct the example clock-names peng.fan
2021-02-25  3:10   ` peng.fan
2021-03-06 20:39   ` Rob Herring
2021-03-06 20:39     ` Rob Herring
2021-02-25  3:10 ` peng.fan [this message]
2021-02-25  3:10   ` [PATCH V3 3/5] arm64: dts: imx8qxp: correct usdhc clock-names sequence peng.fan
2021-02-25  3:10 ` [PATCH V3 4/5] dt-bindings: mmc: fsl-imx-esdhc: add clock bindings peng.fan
2021-02-25  3:10   ` peng.fan
2021-03-04 22:48   ` Rob Herring
2021-03-04 22:48     ` Rob Herring
2021-03-05  0:38     ` Peng Fan
2021-03-05  0:38       ` Peng Fan
2021-03-05 14:09   ` Aisheng Dong
2021-03-05 14:09     ` Aisheng Dong
2021-03-05 14:14     ` Rob Herring
2021-03-05 14:14       ` Rob Herring
2021-03-06  4:53       ` Aisheng Dong
2021-03-06  4:53         ` Aisheng Dong
2021-02-25  3:10 ` [PATCH V3 5/5] mmc: sdhci-esdhc-imx: validate pinctrl before use it peng.fan
2021-02-25  3:10   ` peng.fan
2021-03-02 10:39 ` [PATCH V3 0/5] imx esdhc dt/driver update Ulf Hansson
2021-03-02 10:39   ` Ulf Hansson
2021-03-03  3:00   ` Peng Fan (OSS)
2021-03-03  3:00     ` Peng Fan (OSS)
2021-03-08  0:51     ` Shawn Guo
2021-03-08  0:51       ` Shawn Guo

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