From: Weili Qian <qianweili@huawei.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>
Cc: <linux-kernel@vger.kernel.org>, <linux-crypto@vger.kernel.org>,
<xuzaibo@huawei.com>, <wangzhou1@hisilicon.com>,
<liulongfang@huawei.com>, Weili Qian <qianweili@huawei.com>
Subject: [PATCH 3/4] crypto: hisilicon - add new error type for SEC
Date: Mon, 12 Apr 2021 20:31:34 +0800 [thread overview]
Message-ID: <1618230695-22775-4-git-send-email-qianweili@huawei.com> (raw)
In-Reply-To: <1618230695-22775-1-git-send-email-qianweili@huawei.com>
Kunpeng930 SEC adds several new hardware error types. This patch enables
the new error types and configures the error types as NFE.
Signed-off-by: Weili Qian <qianweili@huawei.com>
---
drivers/crypto/hisilicon/sec2/sec_main.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 26b9904..6f0062d 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -42,8 +42,8 @@
#define SEC_ECC_NUM 16
#define SEC_ECC_MASH 0xFF
#define SEC_CORE_INT_DISABLE 0x0
-#define SEC_CORE_INT_ENABLE 0x1ff
-#define SEC_CORE_INT_CLEAR 0x1ff
+#define SEC_CORE_INT_ENABLE 0x7c1ff
+#define SEC_CORE_INT_CLEAR 0x7c1ff
#define SEC_SAA_ENABLE 0x17f
#define SEC_RAS_CE_REG 0x301050
@@ -51,7 +51,7 @@
#define SEC_RAS_NFE_REG 0x301058
#define SEC_RAS_CE_ENB_MSK 0x88
#define SEC_RAS_FE_ENB_MSK 0x0
-#define SEC_RAS_NFE_ENB_MSK 0x177
+#define SEC_RAS_NFE_ENB_MSK 0x7c177
#define SEC_RAS_DISABLE 0x0
#define SEC_MEM_START_INIT_REG 0x301100
#define SEC_MEM_INIT_DONE_REG 0x301104
@@ -147,6 +147,26 @@ static const struct sec_hw_error sec_hw_errors[] = {
.int_msk = BIT(8),
.msg = "sec_chain_buff_err_rint"
},
+ {
+ .int_msk = BIT(14),
+ .msg = "sec_no_secure_access"
+ },
+ {
+ .int_msk = BIT(15),
+ .msg = "sec_wrapping_key_auth_err"
+ },
+ {
+ .int_msk = BIT(16),
+ .msg = "sec_km_key_crc_fail"
+ },
+ {
+ .int_msk = BIT(17),
+ .msg = "sec_axi_poison_err"
+ },
+ {
+ .int_msk = BIT(18),
+ .msg = "sec_sva_err"
+ },
{}
};
--
2.8.1
next prev parent reply other threads:[~2021-04-12 12:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 12:31 [PATCH 0/4] crypto: hisilicon - adapt hardware error type Weili Qian
2021-04-12 12:31 ` [PATCH 1/4] crypto: hisilicon - dynamic configuration 'err_info' Weili Qian
2021-04-12 12:31 ` [PATCH 2/4] crypto: hisilicon - support new error types for ZIP Weili Qian
2021-04-12 12:31 ` Weili Qian [this message]
2021-04-12 12:31 ` [PATCH 4/4] crypto: hisilicon - enable new error types for QM Weili Qian
2021-04-22 7:45 ` [PATCH 0/4] crypto: hisilicon - adapt hardware error type Herbert Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1618230695-22775-4-git-send-email-qianweili@huawei.com \
--to=qianweili@huawei.com \
--cc=davem@davemloft.net \
--cc=herbert@gondor.apana.org.au \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=liulongfang@huawei.com \
--cc=wangzhou1@hisilicon.com \
--cc=xuzaibo@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.