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From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
	<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
	<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
	<stefanc@marvell.com>, <oferh@marvell.com>, <bpeled@marvell.com>
Subject: [”PATCH” 4/5] arm64: dts: marvell: add pcie mac reset to pcie
Date: Mon, 12 Apr 2021 18:30:55 +0300	[thread overview]
Message-ID: <1618241456-27200-5-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com>

From: Ben Peled <bpeled@marvell.com>

Add system controller and reset bit to each pcie to enable pcie mac reset

Signed-off-by: Ben Peled <bpeled@marvell.com>
---
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 9dcf16b..eb60e73 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -11,6 +11,7 @@
 #include "armada-common.dtsi"
 
 #define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
+#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n)	(0x1 << 11 + ((n + 2) % 3))
 
 / {
 	/*
@@ -513,6 +514,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(0)>;
 		status = "disabled";
 	};
 
@@ -538,6 +541,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(1)>;
 		status = "disabled";
 	};
 
@@ -563,6 +568,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(2)>;
 		status = "disabled";
 	};
 };
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
	<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
	<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
	<stefanc@marvell.com>, <oferh@marvell.com>, <bpeled@marvell.com>
Subject: [”PATCH” 4/5] arm64: dts: marvell: add pcie mac reset to pcie
Date: Mon, 12 Apr 2021 18:30:55 +0300	[thread overview]
Message-ID: <1618241456-27200-5-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com>

From: Ben Peled <bpeled@marvell.com>

Add system controller and reset bit to each pcie to enable pcie mac reset

Signed-off-by: Ben Peled <bpeled@marvell.com>
---
 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 9dcf16b..eb60e73 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -11,6 +11,7 @@
 #include "armada-common.dtsi"
 
 #define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
+#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n)	(0x1 << 11 + ((n + 2) % 3))
 
 / {
 	/*
@@ -513,6 +514,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(0)>;
 		status = "disabled";
 	};
 
@@ -538,6 +541,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(1)>;
 		status = "disabled";
 	};
 
@@ -563,6 +568,8 @@
 		num-lanes = <1>;
 		clock-names = "core", "reg";
 		clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
+		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+		marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(2)>;
 		status = "disabled";
 	};
 };
-- 
2.7.4


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  parent reply	other threads:[~2021-04-12 15:31 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12 15:30 [”PATCH” 0/5] Asynchronous linkdown recovery bpeled
2021-04-12 15:30 ` bpeled
2021-04-12 15:30 ` [”PATCH” 1/5] PCI: armada8k: Disable LTSSM on link down interrupts bpeled
2021-04-12 15:30   ` bpeled
2021-04-12 15:30 ` [”PATCH” 2/5] PCI: armada8k: Add link-down handle bpeled
2021-04-12 15:30   ` bpeled
2021-04-14 12:42   ` Jonathan Cameron
2021-04-14 12:42     ` Jonathan Cameron
2021-04-27  7:07     ` [EXT] " Ben Peled
2021-04-27  7:07       ` Ben Peled
2021-04-12 15:30 ` [”PATCH” 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings bpeled
2021-04-12 15:30   ` bpeled
2021-04-13 15:10   ` Rob Herring
2021-04-13 15:10     ` Rob Herring
2021-04-26 15:58     ` [EXT] " Ben Peled
2021-04-26 15:58       ` Ben Peled
2021-04-12 15:30 ` bpeled [this message]
2021-04-12 15:30   ` [”PATCH” 4/5] arm64: dts: marvell: add pcie mac reset to pcie bpeled
2021-04-12 15:30 ` [”PATCH” 5/5] PCI: armada8k: add device reset to link-down handle bpeled
2021-04-12 15:30   ` bpeled
2021-04-13 10:14 ` [”PATCH” 0/5] Asynchronous linkdown recovery Ben Peled
2021-04-13 10:14   ` Ben Peled

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