From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: tsbogend@alpha.franken.de, paul@crapouillou.net, robh+dt@kernel.org
Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com
Subject: [PATCH 1/4] MIPS: X1830: Respect cell count of common properties.
Date: Tue, 22 Jun 2021 15:37:22 +0800 [thread overview]
Message-ID: <1624347445-88070-2-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1624347445-88070-1-git-send-email-zhouyanjie@wanyeetech.com>
If N fields of X cells should be provided, then that's what the
devicetree should represent, instead of having one single field of
(N * X) cells.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index b21c930..59ca3a8 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -97,9 +97,9 @@
#clock-cells = <1>;
- clocks = <&cgu X1830_CLK_RTCLK
- &cgu X1830_CLK_EXCLK
- &cgu X1830_CLK_PCLK>;
+ clocks = <&cgu X1830_CLK_RTCLK>,
+ <&cgu X1830_CLK_EXCLK>,
+ <&cgu X1830_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@@ -274,8 +274,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
- reg = <0x13420000 0x400
- 0x13421000 0x40>;
+ reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
--
2.7.4
next prev parent reply other threads:[~2021-06-22 7:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-22 7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 7:37 ` 周琰杰 (Zhou Yanjie) [this message]
2021-06-22 12:30 ` [PATCH 1/4] MIPS: X1830: Respect cell count of common properties Paul Cercueil
2021-06-22 7:37 ` [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-22 12:31 ` Paul Cercueil
2021-06-22 7:37 ` [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree 周琰杰 (Zhou Yanjie)
2021-06-22 12:46 ` Paul Cercueil
2021-06-22 13:51 ` 周琰杰
2021-06-22 14:05 ` Paul Cercueil
2021-06-22 14:41 ` 周琰杰
2021-06-22 7:37 ` [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
2021-06-22 12:39 ` Paul Cercueil
2021-06-22 13:55 ` 周琰杰
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