From: Guangbin Huang <huangguangbin2@huawei.com> To: <davem@davemloft.net>, <kuba@kernel.org>, <catalin.marinas@arm.com>, <will@kernel.org>, <maz@kernel.org>, <mark.rutland@arm.com>, <dbrazdil@google.com>, <qperret@google.com> Cc: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <lipeng321@huawei.com>, <huangguangbin2@huawei.com> Subject: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Date: Fri, 30 Jul 2021 11:14:22 +0800 [thread overview] Message-ID: <1627614864-50824-3-git-send-email-huangguangbin2@huawei.com> (raw) In-Reply-To: <1627614864-50824-1-git-send-email-huangguangbin2@huawei.com> From: Xiongfeng Wang <wangxiongfeng2@huawei.com> Device registers can be mapped as write-combine type. In this case, data are not written into the device immediately. They are temporarily stored in the write combine buffer and written into the device when the buffer is full. But in some situation, we need to flush the write combine buffer to device immediately for better performance. So we add a general function called 'flush_wc_write()'. We use DGH instruction to implement this function for ARM64. Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> --- arch/arm64/include/asm/io.h | 2 ++ include/linux/io.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 7fd836bea7eb..5315d023b2dd 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -112,6 +112,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define __iowmb() dma_wmb() #define __iomb() dma_mb() +#define flush_wc_write() dgh() + /* * Relaxed I/O memory access primitives. These follow the Device memory * ordering rules but do not guarantee any ordering relative to Normal memory diff --git a/include/linux/io.h b/include/linux/io.h index 9595151d800d..469d53444218 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -166,4 +166,10 @@ static inline void arch_io_free_memtype_wc(resource_size_t base, } #endif +/* IO barriers */ + +#ifndef flush_wc_write +#define flush_wc_write() do { } while (0) +#endif + #endif /* _LINUX_IO_H */ -- 2.8.1
WARNING: multiple messages have this Message-ID (diff)
From: Guangbin Huang <huangguangbin2@huawei.com> To: <davem@davemloft.net>, <kuba@kernel.org>, <catalin.marinas@arm.com>, <will@kernel.org>, <maz@kernel.org>, <mark.rutland@arm.com>, <dbrazdil@google.com>, <qperret@google.com> Cc: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <lipeng321@huawei.com>, <huangguangbin2@huawei.com> Subject: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Date: Fri, 30 Jul 2021 11:14:22 +0800 [thread overview] Message-ID: <1627614864-50824-3-git-send-email-huangguangbin2@huawei.com> (raw) In-Reply-To: <1627614864-50824-1-git-send-email-huangguangbin2@huawei.com> From: Xiongfeng Wang <wangxiongfeng2@huawei.com> Device registers can be mapped as write-combine type. In this case, data are not written into the device immediately. They are temporarily stored in the write combine buffer and written into the device when the buffer is full. But in some situation, we need to flush the write combine buffer to device immediately for better performance. So we add a general function called 'flush_wc_write()'. We use DGH instruction to implement this function for ARM64. Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> --- arch/arm64/include/asm/io.h | 2 ++ include/linux/io.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 7fd836bea7eb..5315d023b2dd 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -112,6 +112,8 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #define __iowmb() dma_wmb() #define __iomb() dma_mb() +#define flush_wc_write() dgh() + /* * Relaxed I/O memory access primitives. These follow the Device memory * ordering rules but do not guarantee any ordering relative to Normal memory diff --git a/include/linux/io.h b/include/linux/io.h index 9595151d800d..469d53444218 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -166,4 +166,10 @@ static inline void arch_io_free_memtype_wc(resource_size_t base, } #endif +/* IO barriers */ + +#ifndef flush_wc_write +#define flush_wc_write() do { } while (0) +#endif + #endif /* _LINUX_IO_H */ -- 2.8.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-30 3:18 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-30 3:14 [PATCH net-next 0/4] net: hns3: add support for TX push Guangbin Huang 2021-07-30 3:14 ` Guangbin Huang 2021-07-30 3:14 ` [PATCH net-next 1/4] arm64: barrier: add DGH macros to control memory accesses merging Guangbin Huang 2021-07-30 3:14 ` Guangbin Huang 2021-07-30 9:39 ` Catalin Marinas 2021-07-30 9:39 ` Catalin Marinas 2021-07-30 3:14 ` Guangbin Huang [this message] 2021-07-30 3:14 ` [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Guangbin Huang 2021-07-30 9:00 ` Will Deacon 2021-07-30 9:00 ` Will Deacon 2021-10-11 13:37 ` huangguangbin (A) 2021-10-11 13:37 ` huangguangbin (A) 2021-10-15 1:48 ` Xiongfeng Wang 2021-10-15 1:48 ` Xiongfeng Wang 2021-07-30 9:42 ` Catalin Marinas 2021-07-30 9:42 ` Catalin Marinas 2021-07-30 3:14 ` [PATCH net-next 3/4] net: hns3: add support for TX push mode Guangbin Huang 2021-07-30 3:14 ` Guangbin Huang 2021-07-30 3:14 ` [PATCH net-next 4/4] net: hns3: add ethtool priv-flag for TX push Guangbin Huang 2021-07-30 3:14 ` Guangbin Huang
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