From: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
To: <u-boot@lists.denx.de>
Cc: <lukma@denx.de>, <michal.simek@xilinx.com>, <git@xilinx.com>,
<somaashokreddy@gmail.com>,
T Karthik Reddy <t.karthik.reddy@xilinx.com>,
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Subject: [PATCH] clk: versal: Enable only GATE type clocks
Date: Tue, 28 Sep 2021 11:30:27 +0530 [thread overview]
Message-ID: <1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com> (raw)
From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
---
drivers/clk/clk_versal.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 62523d2909..a9dd57b098 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
- return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+ if (versal_clock_gate(clk_id))
+ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+ return 0;
}
static struct clk_ops versal_clk_ops = {
--
2.17.1
next reply other threads:[~2021-09-28 6:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 6:00 Ashok Reddy Soma [this message]
2021-09-29 13:28 ` [PATCH] clk: versal: Enable only GATE type clocks Michal Simek
[not found] <20210927081110.10528-1-ashok.reddy.soma@xilinx.com>
2021-09-27 8:22 ` Michal Simek
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