From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com>, Jacky Bai <ping.bai@nxp.com> Subject: [PATCH v3 06/11] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl Date: Wed, 6 Oct 2021 16:25:59 +0300 [thread overview] Message-ID: <1633526764-30151-7-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1633526764-30151-1-git-send-email-abel.vesa@nxp.com> From: Jacky Bai <ping.bai@nxp.com> On i.MX8DXL, the LSIO subsystem includes below devices: 1x Inline Encryption Engine (IEE) 1x FlexSPI 4x Pulse Width Modulator (PWM) 5x General Purpose Timer (GPT) 8x GPIO 14x Message Unit (MU) 256KB On-Chip Memory (OCRAM) compared to the common imx8-ss-lsio dtsi, some nodes' interrupt property need to be updated. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..d90602bab384 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ +&lsio_gpio0 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu0 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu1 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu2 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu3 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu4 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu5 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu13 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +}; -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com> To: Rob Herring <robh@kernel.org>, Dong Aisheng <aisheng.dong@nxp.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Fabio Estevam <festevam@gmail.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Abel Vesa <abel.vesa@nxp.com>, Jacky Bai <ping.bai@nxp.com> Subject: [PATCH v3 06/11] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl Date: Wed, 6 Oct 2021 16:25:59 +0300 [thread overview] Message-ID: <1633526764-30151-7-git-send-email-abel.vesa@nxp.com> (raw) In-Reply-To: <1633526764-30151-1-git-send-email-abel.vesa@nxp.com> From: Jacky Bai <ping.bai@nxp.com> On i.MX8DXL, the LSIO subsystem includes below devices: 1x Inline Encryption Engine (IEE) 1x FlexSPI 4x Pulse Width Modulator (PWM) 5x General Purpose Timer (GPT) 8x GPIO 14x Message Unit (MU) 256KB On-Chip Memory (OCRAM) compared to the common imx8-ss-lsio dtsi, some nodes' interrupt property need to be updated. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..d90602bab384 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ +&lsio_gpio0 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu0 { + compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu1 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu2 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu3 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu4 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu5 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lsio_mu13 { + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; +}; -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-06 13:26 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-06 13:25 [PATCH v3 00/11] arm64: dts: Add i.MX8DXL initial support Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` [PATCH v3 01/11] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` [PATCH v3 02/11] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` [PATCH v3 03/11] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` [PATCH v3 04/11] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` [PATCH v3 05/11] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Abel Vesa 2021-10-06 13:25 ` Abel Vesa 2021-10-06 13:25 ` Abel Vesa [this message] 2021-10-06 13:25 ` [PATCH v3 06/11] arm64: dts: freescale: Add lsio " Abel Vesa 2021-10-06 13:26 ` [PATCH v3 07/11] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa 2021-10-06 13:26 ` Abel Vesa 2021-10-06 13:26 ` [PATCH v3 08/11] dt-bindings: fsl: scu: Add i.MX8DXL ocotp binding Abel Vesa 2021-10-06 13:26 ` Abel Vesa 2021-10-14 19:56 ` Rob Herring 2021-10-14 19:56 ` Rob Herring 2021-10-06 13:26 ` [PATCH v3 09/11] dt-bindings: i2c: i2c-imx-lpi2c: Fix dtbs_check compatible oneOf error Abel Vesa 2021-10-06 13:26 ` Abel Vesa 2021-10-14 20:02 ` Rob Herring 2021-10-14 20:02 ` Rob Herring 2021-11-10 15:52 ` Abel Vesa 2021-11-10 15:52 ` Abel Vesa 2021-11-10 17:47 ` Abel Vesa 2021-11-10 17:47 ` Abel Vesa 2021-10-06 13:26 ` [PATCH v3 10/11] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Abel Vesa 2021-10-06 13:26 ` Abel Vesa 2021-10-14 20:03 ` Rob Herring 2021-10-14 20:03 ` Rob Herring 2021-10-06 13:26 ` [PATCH v3 11/11] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa 2021-10-06 13:26 ` Abel Vesa 2021-10-14 20:04 ` Rob Herring 2021-10-14 20:04 ` Rob Herring
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