From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Masami Hiramatsu <mhiramat@kernel.org>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v2 4/8] phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC
Date: Wed, 20 Oct 2021 08:58:04 +0900 [thread overview]
Message-ID: <1634687888-23900-5-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1634687888-23900-1-git-send-email-hayashi.kunihiko@socionext.com>
Add basic support for UniPhier NX1 SoC. This includes a compatible string,
SoC-dependent data, and a function that set to 2-lane mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index 6bdbd1f214dd..fde8aac5f4b6 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -39,6 +39,10 @@
#define SG_USBPCIESEL 0x590
#define SG_USBPCIESEL_PCIE BIT(0)
+/* SC */
+#define SC_US3SRCSEL 0x2244
+#define SC_US3SRCSEL_2LANE GENMASK(9, 8)
+
#define PCL_PHY_R00 0
#define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
#define PCL_PHY_R06 6
@@ -261,6 +265,12 @@ static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
}
+static void uniphier_pciephy_nx1_setmode(struct regmap *regmap)
+{
+ regmap_update_bits(regmap, SC_US3SRCSEL,
+ SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE);
+}
+
static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
.is_legacy = true,
};
@@ -274,6 +284,11 @@ static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
.is_legacy = false,
};
+static const struct uniphier_pciephy_soc_data uniphier_nx1_data = {
+ .is_legacy = false,
+ .set_phymode = uniphier_pciephy_nx1_setmode,
+};
+
static const struct of_device_id uniphier_pciephy_match[] = {
{
.compatible = "socionext,uniphier-pro5-pcie-phy",
@@ -287,6 +302,10 @@ static const struct of_device_id uniphier_pciephy_match[] = {
.compatible = "socionext,uniphier-pxs3-pcie-phy",
.data = &uniphier_pxs3_data,
},
+ {
+ .compatible = "socionext,uniphier-nx1-pcie-phy",
+ .data = &uniphier_nx1_data,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Masami Hiramatsu <mhiramat@kernel.org>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v2 4/8] phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC
Date: Wed, 20 Oct 2021 08:58:04 +0900 [thread overview]
Message-ID: <1634687888-23900-5-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1634687888-23900-1-git-send-email-hayashi.kunihiko@socionext.com>
Add basic support for UniPhier NX1 SoC. This includes a compatible string,
SoC-dependent data, and a function that set to 2-lane mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index 6bdbd1f214dd..fde8aac5f4b6 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -39,6 +39,10 @@
#define SG_USBPCIESEL 0x590
#define SG_USBPCIESEL_PCIE BIT(0)
+/* SC */
+#define SC_US3SRCSEL 0x2244
+#define SC_US3SRCSEL_2LANE GENMASK(9, 8)
+
#define PCL_PHY_R00 0
#define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
#define PCL_PHY_R06 6
@@ -261,6 +265,12 @@ static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
}
+static void uniphier_pciephy_nx1_setmode(struct regmap *regmap)
+{
+ regmap_update_bits(regmap, SC_US3SRCSEL,
+ SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE);
+}
+
static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
.is_legacy = true,
};
@@ -274,6 +284,11 @@ static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
.is_legacy = false,
};
+static const struct uniphier_pciephy_soc_data uniphier_nx1_data = {
+ .is_legacy = false,
+ .set_phymode = uniphier_pciephy_nx1_setmode,
+};
+
static const struct of_device_id uniphier_pciephy_match[] = {
{
.compatible = "socionext,uniphier-pro5-pcie-phy",
@@ -287,6 +302,10 @@ static const struct of_device_id uniphier_pciephy_match[] = {
.compatible = "socionext,uniphier-pxs3-pcie-phy",
.data = &uniphier_pxs3_data,
},
+ {
+ .compatible = "socionext,uniphier-nx1-pcie-phy",
+ .data = &uniphier_nx1_data,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Masami Hiramatsu <mhiramat@kernel.org>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v2 4/8] phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC
Date: Wed, 20 Oct 2021 08:58:04 +0900 [thread overview]
Message-ID: <1634687888-23900-5-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1634687888-23900-1-git-send-email-hayashi.kunihiko@socionext.com>
Add basic support for UniPhier NX1 SoC. This includes a compatible string,
SoC-dependent data, and a function that set to 2-lane mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index 6bdbd1f214dd..fde8aac5f4b6 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -39,6 +39,10 @@
#define SG_USBPCIESEL 0x590
#define SG_USBPCIESEL_PCIE BIT(0)
+/* SC */
+#define SC_US3SRCSEL 0x2244
+#define SC_US3SRCSEL_2LANE GENMASK(9, 8)
+
#define PCL_PHY_R00 0
#define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
#define PCL_PHY_R06 6
@@ -261,6 +265,12 @@ static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
}
+static void uniphier_pciephy_nx1_setmode(struct regmap *regmap)
+{
+ regmap_update_bits(regmap, SC_US3SRCSEL,
+ SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE);
+}
+
static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
.is_legacy = true,
};
@@ -274,6 +284,11 @@ static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
.is_legacy = false,
};
+static const struct uniphier_pciephy_soc_data uniphier_nx1_data = {
+ .is_legacy = false,
+ .set_phymode = uniphier_pciephy_nx1_setmode,
+};
+
static const struct of_device_id uniphier_pciephy_match[] = {
{
.compatible = "socionext,uniphier-pro5-pcie-phy",
@@ -287,6 +302,10 @@ static const struct of_device_id uniphier_pciephy_match[] = {
.compatible = "socionext,uniphier-pxs3-pcie-phy",
.data = &uniphier_pxs3_data,
},
+ {
+ .compatible = "socionext,uniphier-nx1-pcie-phy",
+ .data = &uniphier_nx1_data,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2021-10-19 23:58 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 23:58 [PATCH v2 0/8] phy: socionext: Introduce some features for UniPhier SoCs Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 1/8] dt-bindings: phy: uniphier-usb3: Add bindings for NX1 SoC Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-28 21:05 ` Rob Herring
2021-10-28 21:05 ` Rob Herring
2021-10-28 21:05 ` Rob Herring
2021-10-19 23:58 ` [PATCH v2 2/8] phy: uniphier-usb3: Add compatible string " Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 3/8] dt-bindings: phy: uniphier-pcie: Add bindings " Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-28 21:06 ` Rob Herring
2021-10-28 21:06 ` Rob Herring
2021-10-28 21:06 ` Rob Herring
2021-10-19 23:58 ` Kunihiko Hayashi [this message]
2021-10-19 23:58 ` [PATCH v2 4/8] phy: uniphier-pcie: Add compatible string and SoC-dependent data " Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 5/8] phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 6/8] phy: uniphier-pcie: Add dual-phy support for NX1 SoC Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 7/8] dt-bindings: phy: uniphier-ahci: Add bindings for Pro4 SoC Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-28 21:12 ` Rob Herring
2021-10-28 21:12 ` Rob Herring
2021-10-28 21:12 ` Rob Herring
2021-10-29 10:33 ` Kunihiko Hayashi
2021-10-29 10:33 ` Kunihiko Hayashi
2021-10-29 10:33 ` Kunihiko Hayashi
2021-10-19 23:58 ` [PATCH v2 8/8] phy: uniphier-ahci: Add support " Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
2021-10-19 23:58 ` Kunihiko Hayashi
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