From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>,
richard.henderson@linaro.org, laurent@vivier.eu
Subject: [PATCH v12 07/26] target/loongarch: Add fixed point load/store instruction translation
Date: Wed, 1 Dec 2021 16:16:06 +0800 [thread overview]
Message-ID: <1638346585-3436-8-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1638346585-3436-1-git-send-email-gaosong@loongson.cn>
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/helper.h | 3 +
target/loongarch/insn_trans/trans_memory.c.inc | 229 +++++++++++++++++++++++++
target/loongarch/insns.decode | 55 ++++++
target/loongarch/op_helper.c | 15 ++
target/loongarch/translate.c | 6 +
5 files changed, 308 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_memory.c.inc
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 04e0245..100622b 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -8,3 +8,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
DEF_HELPER_FLAGS_1(bitrev_w, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(bitrev_d, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
+
+DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl)
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
new file mode 100644
index 0000000..9003d9a
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+
+ return true;
+}
+
+static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+
+ return true;
+}
+
+static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ return true;
+}
+
+static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ return true;
+}
+
+static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
+
+ return true;
+}
+
+static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
+{
+ TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
+
+ return true;
+}
+
+static bool trans_preld(DisasContext *ctx, arg_preld *a)
+{
+ return true;
+}
+
+static bool trans_dbar(DisasContext *ctx, arg_dbar * a)
+{
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
+ return true;
+}
+
+static bool trans_ibar(DisasContext *ctx, arg_ibar *a)
+{
+ ctx->base.is_jmp = DISAS_STOP;
+ return true;
+}
+
+static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+
+ return true;
+}
+
+static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->im);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+
+ return true;
+}
+
+TRANS(ld_b, gen_load, MO_SB)
+TRANS(ld_h, gen_load, MO_TESW)
+TRANS(ld_w, gen_load, MO_TESL)
+TRANS(ld_d, gen_load, MO_TEQ)
+TRANS(st_b, gen_store, MO_SB)
+TRANS(st_h, gen_store, MO_TESW)
+TRANS(st_w, gen_store, MO_TESL)
+TRANS(st_d, gen_store, MO_TEQ)
+TRANS(ld_bu, gen_load, MO_UB)
+TRANS(ld_hu, gen_load, MO_TEUW)
+TRANS(ld_wu, gen_load, MO_TEUL)
+TRANS(ldx_b, gen_loadx, MO_SB)
+TRANS(ldx_h, gen_loadx, MO_TESW)
+TRANS(ldx_w, gen_loadx, MO_TESL)
+TRANS(ldx_d, gen_loadx, MO_TEQ)
+TRANS(stx_b, gen_storex, MO_SB)
+TRANS(stx_h, gen_storex, MO_TESW)
+TRANS(stx_w, gen_storex, MO_TESL)
+TRANS(stx_d, gen_storex, MO_TEQ)
+TRANS(ldx_bu, gen_loadx, MO_UB)
+TRANS(ldx_hu, gen_loadx, MO_TEUW)
+TRANS(ldx_wu, gen_loadx, MO_TEUL)
+TRANS(ldptr_w, gen_ldptr, MO_TESL)
+TRANS(stptr_w, gen_stptr, MO_TESL)
+TRANS(ldptr_d, gen_ldptr, MO_TEQ)
+TRANS(stptr_d, gen_stptr, MO_TEQ)
+TRANS(ldgt_b, gen_load_gt, MO_SB)
+TRANS(ldgt_h, gen_load_gt, MO_TESW)
+TRANS(ldgt_w, gen_load_gt, MO_TESL)
+TRANS(ldgt_d, gen_load_gt, MO_TEQ)
+TRANS(ldle_b, gen_load_le, MO_SB)
+TRANS(ldle_h, gen_load_le, MO_TESW)
+TRANS(ldle_w, gen_load_le, MO_TESL)
+TRANS(ldle_d, gen_load_le, MO_TEQ)
+TRANS(stgt_b, gen_store_gt, MO_SB)
+TRANS(stgt_h, gen_store_gt, MO_TESW)
+TRANS(stgt_w, gen_store_gt, MO_TESL)
+TRANS(stgt_d, gen_store_gt, MO_TEQ)
+TRANS(stle_b, gen_store_le, MO_SB)
+TRANS(stle_h, gen_store_le, MO_TESW)
+TRANS(stle_w, gen_store_le, MO_TESL)
+TRANS(stle_d, gen_store_le, MO_TEQ)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index b0bed55..1156e69 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -8,21 +8,25 @@
#
# Fields
#
+%i14s2 10:s14 !function=shl_2
%sa2p1 15:2 !function=plus_1
#
# Argument sets
#
+&i imm
&r_i rd imm
&rr rd rj
&rrr rd rj rk
&rr_i rd rj imm
+&hint_r_i hint rj imm
&rrr_sa rd rj rk sa
&rr_ms_ls rd rj ms ls
#
# Formats
#
+@i15 .... ........ ..... imm:15 &i
@rr .... ........ ..... ..... rj:5 rd:5 &rr
@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
@r_i20 .... ... imm:s20 rd:5 &r_i
@@ -30,7 +34,9 @@
@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
+@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
+@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
@@ -138,3 +144,52 @@ bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw
bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw
bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd
bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd
+
+#
+# Fixed point load/store instruction
+#
+ld_b 0010 100000 ............ ..... ..... @rr_i12
+ld_h 0010 100001 ............ ..... ..... @rr_i12
+ld_w 0010 100010 ............ ..... ..... @rr_i12
+ld_d 0010 100011 ............ ..... ..... @rr_i12
+st_b 0010 100100 ............ ..... ..... @rr_i12
+st_h 0010 100101 ............ ..... ..... @rr_i12
+st_w 0010 100110 ............ ..... ..... @rr_i12
+st_d 0010 100111 ............ ..... ..... @rr_i12
+ld_bu 0010 101000 ............ ..... ..... @rr_i12
+ld_hu 0010 101001 ............ ..... ..... @rr_i12
+ld_wu 0010 101010 ............ ..... ..... @rr_i12
+ldx_b 0011 10000000 00000 ..... ..... ..... @rrr
+ldx_h 0011 10000000 01000 ..... ..... ..... @rrr
+ldx_w 0011 10000000 10000 ..... ..... ..... @rrr
+ldx_d 0011 10000000 11000 ..... ..... ..... @rrr
+stx_b 0011 10000001 00000 ..... ..... ..... @rrr
+stx_h 0011 10000001 01000 ..... ..... ..... @rrr
+stx_w 0011 10000001 10000 ..... ..... ..... @rrr
+stx_d 0011 10000001 11000 ..... ..... ..... @rrr
+ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
+ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
+ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
+preld 0010 101011 ............ ..... ..... @hint_r_i12
+dbar 0011 10000111 00100 ............... @i15
+ibar 0011 10000111 00101 ............... @i15
+ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2
+stptr_w 0010 0101 .............. ..... ..... @rr_i14s2
+ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2
+stptr_d 0010 0111 .............. ..... ..... @rr_i14s2
+ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr
+ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr
+ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr
+ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr
+ldle_b 0011 10000111 10100 ..... ..... ..... @rrr
+ldle_h 0011 10000111 10101 ..... ..... ..... @rrr
+ldle_w 0011 10000111 10110 ..... ..... ..... @rrr
+ldle_d 0011 10000111 10111 ..... ..... ..... @rrr
+stgt_b 0011 10000111 11000 ..... ..... ..... @rrr
+stgt_h 0011 10000111 11001 ..... ..... ..... @rrr
+stgt_w 0011 10000111 11010 ..... ..... ..... @rrr
+stgt_d 0011 10000111 11011 ..... ..... ..... @rrr
+stle_b 0011 10000111 11100 ..... ..... ..... @rrr
+stle_h 0011 10000111 11101 ..... ..... ..... @rrr
+stle_w 0011 10000111 11110 ..... ..... ..... @rrr
+stle_d 0011 10000111 11111 ..... ..... ..... @rrr
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index 1fc9d81..53ee9ff 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -41,3 +41,18 @@ target_ulong helper_bitswap(target_ulong v)
((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
return v;
}
+
+/* loongarch assert op */
+void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
+{
+ if (rj > rk) {
+ do_raise_exception(env, EXCP_ADE, GETPC());
+ }
+}
+
+void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
+{
+ if (rj <= rk) {
+ do_raise_exception(env, EXCP_ADE, GETPC());
+ }
+}
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index c0875db..4ce452a 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -31,6 +31,11 @@ static inline int plus_1(DisasContext *ctx, int x)
return x + 1;
}
+static inline int shl_2(DisasContext *ctx, int x)
+{
+ return x * 4;
+}
+
void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
@@ -148,6 +153,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
#include "insn_trans/trans_bit.c.inc"
+#include "insn_trans/trans_memory.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-12-01 8:27 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 8:15 [PATCH v12 00/26] Add LoongArch linux-user emulation support Song Gao
2021-12-01 8:16 ` [PATCH v12 01/26] target/loongarch: Add README Song Gao
2021-12-01 8:16 ` [PATCH v12 02/26] target/loongarch: Add core definition Song Gao
2021-12-01 8:16 ` [PATCH v12 03/26] target/loongarch: Add main translation routines Song Gao
2021-12-01 8:16 ` [PATCH v12 04/26] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-12-01 8:16 ` [PATCH v12 05/26] target/loongarch: Add fixed point shift " Song Gao
2021-12-01 8:16 ` [PATCH v12 06/26] target/loongarch: Add fixed point bit " Song Gao
2021-12-01 8:16 ` Song Gao [this message]
2021-12-01 8:16 ` [PATCH v12 08/26] target/loongarch: Add fixed point atomic " Song Gao
2021-12-01 21:22 ` Richard Henderson
2021-12-01 8:16 ` [PATCH v12 09/26] target/loongarch: Add fixed point extra " Song Gao
2021-12-01 8:16 ` [PATCH v12 10/26] target/loongarch: Add floating point arithmetic " Song Gao
2021-12-01 8:16 ` [PATCH v12 11/26] target/loongarch: Add floating point comparison " Song Gao
2021-12-01 8:16 ` [PATCH v12 12/26] target/loongarch: Add floating point conversion " Song Gao
2021-12-01 8:16 ` [PATCH v12 13/26] target/loongarch: Add floating point move " Song Gao
2021-12-01 8:16 ` [PATCH v12 14/26] target/loongarch: Add floating point load/store " Song Gao
2021-12-01 8:16 ` [PATCH v12 15/26] target/loongarch: Add branch " Song Gao
2021-12-01 8:16 ` [PATCH v12 16/26] target/loongarch: Add disassembler Song Gao
2021-12-01 21:28 ` Richard Henderson
2021-12-01 8:16 ` [PATCH v12 17/26] linux-user: Add LoongArch generic header files Song Gao
2021-12-01 8:16 ` [PATCH v12 18/26] linux-user: Add LoongArch specific structures Song Gao
2021-12-01 8:16 ` [PATCH v12 19/26] linux-user: Add LoongArch signal support Song Gao
2021-12-01 8:16 ` [PATCH v12 20/26] linux-user: Add LoongArch elf support Song Gao
2021-12-01 8:16 ` [PATCH v12 21/26] linux-user: Add LoongArch syscall support Song Gao
2021-12-01 8:16 ` [PATCH v12 22/26] linux-user: Add LoongArch cpu_loop support Song Gao
2021-12-01 8:16 ` [PATCH v12 23/26] default-configs: Add loongarch linux-user support Song Gao
2021-12-01 8:16 ` [PATCH v12 24/26] target/loongarch: Add target build suport Song Gao
2021-12-01 8:16 ` [PATCH v12 25/26] target/loongarch: 'make check-tcg' support Song Gao
2021-12-01 8:16 ` [PATCH v12 26/26] scripts: add loongarch64 binfmt config Song Gao
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